// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// c5: c_us 
// c6: c_us 
// c7: c_us 
// e1: sn7400 
module m217x (ac0, ac1, ac2, ac2bufl, ac3, buf2ac, bus0, bus1, bus2, bus3, clrbufl, clrclkl, cnt2bufh, count, loadclkh, n_t_12x, n_t_13x, n_t_14x, n_t_15x, n_t_16x, n_t_17x, n_t_18x, n_t_19x, n_t_1x, n_t_2x, n_t_31x, n_t_32x, n_t_33x, n_t_35x, n_t_37x, n_t_38x);
input ac0;
input ac1;
input ac2;
input ac2bufl;
input ac3;
input buf2ac;
output bus0;
output bus1;
output bus2;
output bus3;
input clrbufl;
input clrclkl;
input cnt2bufh;
input count;
input loadclkh;
inout reg n_t_12x;
output n_t_13x;
inout reg n_t_14x;
output n_t_15x;
inout reg n_t_16x;
output n_t_17x;
inout reg n_t_18x;
output n_t_19x;
inout reg n_t_1x;
inout reg n_t_2x;
inout n_t_31x;
inout reg n_t_32x;
inout n_t_33x;
inout n_t_35x;
inout reg n_t_37x;
inout n_t_38x;

reg n_t_12x_m;
reg n_t_14x_m;
reg n_t_16x_m;
reg n_t_18x_m;
reg n_t_1x_m;
reg n_t_2x_m;
reg n_t_32x_m;
reg n_t_37x_m;

wire n_t_26x;
wire n_t_27x;
wire n_t_28x;
wire n_t_29x;
wire n_t_6x;
wire n_t_7x;
wire n_t_8x;
wire n_t_9x;
assign n_t_7x = ~(ac2bufl & ac2);
assign n_t_6x = ~(ac2bufl & ac3);
assign n_t_9x = ~(ac0 & ac2bufl);
assign n_t_8x = ~(ac1 & ac2bufl);
// e2: sn7474 
always @(n_t_33x, clrclkl, n_t_28x, n_t_35x)
  if (~clrclkl) begin
    n_t_2x_m <= 1'b0;
  end else
  if (~n_t_28x) begin
    n_t_2x_m <= 1'b1;
  end else
  if (~(n_t_33x)) begin
    n_t_2x_m <= n_t_35x;
  end
always @(n_t_33x, clrclkl, n_t_28x, n_t_2x_m)
  if (~clrclkl) begin
    n_t_2x <= 1'b0;
  end else
  if (~n_t_28x) begin
    n_t_2x <= 1'b1;
  end else
  if (n_t_33x) begin
    n_t_2x <= n_t_2x_m;
  end
assign n_t_35x = ~n_t_2x;
always @(n_t_35x, clrclkl, n_t_29x, n_t_38x)
  if (~clrclkl) begin
    n_t_37x_m <= 1'b0;
  end else
  if (~n_t_29x) begin
    n_t_37x_m <= 1'b1;
  end else
  if (~(n_t_35x)) begin
    n_t_37x_m <= n_t_38x;
  end
always @(n_t_35x, clrclkl, n_t_29x, n_t_37x_m)
  if (~clrclkl) begin
    n_t_37x <= 1'b0;
  end else
  if (~n_t_29x) begin
    n_t_37x <= 1'b1;
  end else
  if (n_t_35x) begin
    n_t_37x <= n_t_37x_m;
  end
assign n_t_38x = ~n_t_37x;
// e3: sn7401 
// bus3 = !(n_t_18x & buf2ac); 
// bus2 = !(n_t_16x & buf2ac); 
// bus0 = !(n_t_12x & buf2ac); 
// bus1 = !(buf2ac & n_t_14x); 
// e4: sn7400 
assign n_t_26x = ~(n_t_18x & loadclkh);
assign n_t_27x = ~(n_t_16x & loadclkh);
assign n_t_29x = ~(n_t_12x & loadclkh);
assign n_t_28x = ~(loadclkh & n_t_14x);
// e5: sn7474 
always @(cnt2bufh, clrbufl, n_t_8x, n_t_2x)
  if (~clrbufl) begin
    n_t_14x_m <= 1'b0;
  end else
  if (~n_t_8x) begin
    n_t_14x_m <= 1'b1;
  end else
  if (~(cnt2bufh)) begin
    n_t_14x_m <= n_t_2x;
  end
always @(cnt2bufh, clrbufl, n_t_8x, n_t_14x_m)
  if (~clrbufl) begin
    n_t_14x <= 1'b0;
  end else
  if (~n_t_8x) begin
    n_t_14x <= 1'b1;
  end else
  if (cnt2bufh) begin
    n_t_14x <= n_t_14x_m;
  end
assign n_t_15x = ~n_t_14x;
always @(cnt2bufh, clrbufl, n_t_9x, n_t_37x)
  if (~clrbufl) begin
    n_t_12x_m <= 1'b0;
  end else
  if (~n_t_9x) begin
    n_t_12x_m <= 1'b1;
  end else
  if (~(cnt2bufh)) begin
    n_t_12x_m <= n_t_37x;
  end
always @(cnt2bufh, clrbufl, n_t_9x, n_t_12x_m)
  if (~clrbufl) begin
    n_t_12x <= 1'b0;
  end else
  if (~n_t_9x) begin
    n_t_12x <= 1'b1;
  end else
  if (cnt2bufh) begin
    n_t_12x <= n_t_12x_m;
  end
assign n_t_13x = ~n_t_12x;
// e6: sn7474 
always @(cnt2bufh, clrbufl, n_t_6x, n_t_32x)
  if (~clrbufl) begin
    n_t_18x_m <= 1'b0;
  end else
  if (~n_t_6x) begin
    n_t_18x_m <= 1'b1;
  end else
  if (~(cnt2bufh)) begin
    n_t_18x_m <= n_t_32x;
  end
always @(cnt2bufh, clrbufl, n_t_6x, n_t_18x_m)
  if (~clrbufl) begin
    n_t_18x <= 1'b0;
  end else
  if (~n_t_6x) begin
    n_t_18x <= 1'b1;
  end else
  if (cnt2bufh) begin
    n_t_18x <= n_t_18x_m;
  end
assign n_t_19x = ~n_t_18x;
always @(cnt2bufh, clrbufl, n_t_7x, n_t_1x)
  if (~clrbufl) begin
    n_t_16x_m <= 1'b0;
  end else
  if (~n_t_7x) begin
    n_t_16x_m <= 1'b1;
  end else
  if (~(cnt2bufh)) begin
    n_t_16x_m <= n_t_1x;
  end
always @(cnt2bufh, clrbufl, n_t_7x, n_t_16x_m)
  if (~clrbufl) begin
    n_t_16x <= 1'b0;
  end else
  if (~n_t_7x) begin
    n_t_16x <= 1'b1;
  end else
  if (cnt2bufh) begin
    n_t_16x <= n_t_16x_m;
  end
assign n_t_17x = ~n_t_16x;
// e7: sn7474 
always @(count, clrclkl, n_t_26x, n_t_31x)
  if (~clrclkl) begin
    n_t_32x_m <= 1'b0;
  end else
  if (~n_t_26x) begin
    n_t_32x_m <= 1'b1;
  end else
  if (~(count)) begin
    n_t_32x_m <= n_t_31x;
  end
always @(count, clrclkl, n_t_26x, n_t_32x_m)
  if (~clrclkl) begin
    n_t_32x <= 1'b0;
  end else
  if (~n_t_26x) begin
    n_t_32x <= 1'b1;
  end else
  if (count) begin
    n_t_32x <= n_t_32x_m;
  end
assign n_t_31x = ~n_t_32x;
always @(n_t_31x, clrclkl, n_t_27x, n_t_33x)
  if (~clrclkl) begin
    n_t_1x_m <= 1'b0;
  end else
  if (~n_t_27x) begin
    n_t_1x_m <= 1'b1;
  end else
  if (~(n_t_31x)) begin
    n_t_1x_m <= n_t_33x;
  end
always @(n_t_31x, clrclkl, n_t_27x, n_t_1x_m)
  if (~clrclkl) begin
    n_t_1x <= 1'b0;
  end else
  if (~n_t_27x) begin
    n_t_1x <= 1'b1;
  end else
  if (n_t_31x) begin
    n_t_1x <= n_t_1x_m;
  end
assign n_t_33x = ~n_t_1x;
// open collector 'wire-or's 
assign bus0 = (n_t_12x & buf2ac)? 1'b0: 1'bz;
assign bus1 = (buf2ac & n_t_14x)? 1'b0: 1'bz;
assign bus2 = (n_t_16x & buf2ac)? 1'b0: 1'bz;
assign bus3 = (n_t_18x & buf2ac)? 1'b0: 1'bz;
endmodule