~/Verilog/bin/topld.pl M219X
info: cpol_use ne cpol_use20_8axial
info: 74h40n ne 7440n
info: 74h40n ne 7440n
info: 74h30n ne 7430n
info: 74h55n ne 7455n
info: 74h00n ne 7400n
info: 74h10n ne 7410n
info: 74h55n ne 7455n
info: 74h00n ne 7400n
info: 74h72n ne 7472n
info: 74h72n ne 7472n
info: 74h72n ne 7472n
info: 74h00n ne 7400n
info: 74h00n ne 7400n
info: 74h72n ne 7472n
info: 74h72n ne 7472n
info: 74h00n ne 7400n
info: 74h72n ne 7472n
info: 74h72n ne 7472n
info: double ne edge_con4
warning: making u$3/double/ a connector
warning: non-bypass capacitor deleted: c1
warning: non-bypass capacitor deleted: c2
~/Verilog/bin/smaller.pl M219X.PLD >vv || (rm vv; exit 1)
13 signals were removed:
  gdollar_1: !gdollar_0
  gdollar_3: !gdollar_2
  n_t_19x: !n_t_10x
  n_t_27x: !n_t_13x
  n_t_28x: !n_t_12x
  n_t_30x: !n_t_31x
  n_t_32x: !n_t_33x
  n_t_36x: !n_t_37x
  n_t_39x: !n_t_41x
  n_t_58x: !n_t_59x
  n_t_7x: !n_t_3x
  n_t_88x: !n_t_87x
  n_t_93x: !n_t_81x
~/Verilog/bin/smaller.pl vv >M219XX.PLD || (rm M219XX.PLD; exit 1)
0 signals were removed:
~/Verilog/bin/cupl2v.pl M219XX.PLD >vv || (rm vv; exit 1)
no n_t_5x.j at /home/vrs/Verilog/bin/cupl2v.pl line 283, <INPUT> line 544.
../Makefile:29: recipe for target 'M219X.v' failed
make: *** [M219X.v] Error 1
rm M219XX.PLD