Exported from /home/vrs/Eagle/projects/DEC/Mxxx/M220/M220A.sch Part Pad Pin Dir Net C1 + + pas VCC - - pas GND C2 + + pas VCC - - pas GND C3 + + pas VCC - - pas GND C4 + + pas VCC - - pas GND C5 + + pas VCC - - pas GND C6 + + pas VCC - - pas GND C7 + + pas VCC - - pas GND C8 + + pas VCC - - pas GND E1 1 I4 in SHIFT_R1 2 I5 in ADDER0 3 I6 in SHIFT_R2 4 I1 in ADDER2 5 I2 in NO_SHIFT 8 O out AJ1 9 I8 in ADDER3 10 I7 in SHIFT_L1 11 I10 pas N$13 12 I9 pas N$10 13 I3 in ADDER1 E2 1 I4 in SHIFT_R1 2 I5 in ADDER1 3 I6 in SHIFT_R2 4 I1 in ADDER3 5 I2 in NO_SHIFT 8 O out AK2 9 I8 in ADDER4 10 I7 in SHIFT_L1 11 I10 pas N$11 12 I9 pas N$9 13 I3 in ADDER2 E3 1 A in +3V 2 B in +3V 3 C in AND 4 A in ADDER4 5 B in +3V 6 C in +3V 8 D in SHIFT_L2 9 !X out N$10 10 X out N$13 11 X out N$13 12 !X out N$10 13 D in N$1 E4 1 A in +3V 2 B in +3V 3 C in AND 4 A in ADDER5 5 B in +3V 6 C in +3V 8 D in SHIFT_L2 9 !X out N$9 10 X out N$11 11 X out N$11 12 !X out N$9 13 D in N$3 E5 1 I0 in GND 2 I1 in GND 3 O out +3V 8 O out N$3 9 I0 in AC3_H 10 I1 in MB3_H 11 O out N$1 12 I0 in AC2_H 13 I1 in MB2_H E6 2 D in AJ1 3 CLK in AK1 5 Q out MA2_H 6 !Q out MA2_L 8 !Q out MA3_L 9 Q out MA3_H 11 CLK in AK1 12 D in AK2 E7 2 D in AJ1 3 CLK in AN2 5 Q out PC2_H 6 !Q out PC2_L 8 !Q out PC3_L 9 Q out PC3_H 11 CLK in AN2 12 D in AK2 E8 2 D in AJ1 3 CLK in AR1 5 Q out MB2_H 6 !Q out MB2_L 8 !Q out MB3_L 9 Q out MB3_H 11 CLK in AR1 12 D in AK2 E9 1 I0 in MB3_H 2 I1 in MB3_H 4 I2 in MB3_H 5 I3 in MB3_H 6 O out N$15 8 O out AS2 9 I0 in MB3_L 10 I1 in MB3_L 12 I2 in MB3_L 13 I3 in MB3_L E10 1 I0 in MB2_H 2 I1 in MB2_H 4 I2 in MB2_H 5 I3 in MB2_H 6 O out AU2 8 O out AT2 9 I0 in MB2_L 10 I1 in MB2_L 12 I2 in MB2_L 13 I3 in MB2_L E11 1 S1 out ADDER3 2 A1 in N$8 3 B1 in N$14 5 C0 in C0 9 P$2 pas N$5 10 C2 out C2 12 S2 out ADDER2 13 B2 in N$12 14 A2 in N$5 E12 1 I4 in GND 2 I5 in AC2_H 3 I6 in AC_ENABL 4 I1 in AC2_L 5 I2 in !AC_ENABL 9 I8 in MQ2_H 10 I7 in MQ_ENABL 11 I10 pas N$6 12 I9 pas N$7 13 I3 in GND E13 1 I4 in SR_ENABL 2 I5 in SC2 3 I6 in SC_ENABL 4 I1 in DATA2 5 I2 in DATA_ENABL 6 SPARE pas !AC_ENABL 8 O out N$5 9 I8 in IO2 10 I7 in IO_ENABL 11 I10 pas N$6 12 I9 pas N$7 13 I3 in SR2 E14 1 I4 in +3V 2 I5 in AC3_H 3 I6 in AC_ENABL 4 I1 in AC3_L 5 I2 in !AC_ENABL 9 I8 in MQ3_H 10 I7 in MQ_ENABL 11 I10 pas N$4 12 I9 pas N$2 13 I3 in BE2 E15 2 D in AJ1 3 CLK in AU1 5 Q out AC2_H 6 !Q out AC2_L 8 !Q out AC3_L 9 Q out AC3_H 11 CLK in AU1 12 D in AK2 E16 1 I4 in MA_ENABL 2 I5 in PC2_H 3 I6 in PC_ENABL 4 I1 in MEM2 5 I2 in MEM_ENABL 8 O out N$12 9 I8 in DA2 10 I7 in DA_ENABL 13 I3 in MA2_H E17 1 I4 in BR2 2 I5 in PC3_H 3 I6 in PC_ENABL 4 I1 in BV2 5 I2 in BV1 8 O out N$14 9 I8 in BU1 10 I7 in DA_ENABL 13 I3 in MA3_H E18 1 I4 in SR_ENABL 2 I5 in SC3 3 I6 in SC_ENABL 4 I1 in DATA3 5 I2 in DATA_ENABL 8 O out N$8 9 I8 in IO3 10 I7 in IO_ENABL 11 I10 pas N$4 12 I9 pas N$2 13 I3 in SR3 R1 1 1 pas MEM2 2 2 pas VCC R2 1 1 pas BV2 2 2 pas VCC U$1 AA1 1 io AND AA2 1 io VCC AB1 1 io ADDER0 AC1 1 io ADDER1 AC2 1 io GND AD1 1 io SHIFT_R2 AD2 1 io SHIFT_R1 AE1 1 io NO_SHIFT AE2 1 io ADDER2 AF1 1 io ADDER3 AF2 1 io SHIFT_L1 AH1 1 io SHIFT_L2 AH2 1 io ADDER4 AJ1 1 io AJ1 AJ2 1 io ADDER5 AK1 1 io AK1 AK2 1 io AK2 AL1 1 io MA3_L AL2 1 io MA3_H AM1 1 io MA2_L AM2 1 io MA2_H AN1 1 io PC3_H AN2 1 io AN2 AP1 1 io PC2_H AP2 1 io PC3_L AR1 1 io AR1 AR2 1 io PC2_L AS1 1 io N$15 AS2 1 io AS2 AT1 1 io GND AT2 1 io AT2 AU1 1 io AU1 AU2 1 io AU2 AV1 1 io AC3_H AV2 1 io AC3_L BA1 1 io AC2_H BA2 1 io VCC BB1 1 io AC2_L BC1 1 io SR_ENABL BC2 1 io GND BD1 1 io SC2 BD2 1 io SR3 BE1 1 io SR2 BE2 1 io BE2 BF1 1 io MQ_ENABL BF2 1 io SC_ENABL BH1 1 io MQ2_H BH2 1 io AC_ENABL BJ1 1 io C0 BJ2 1 io !AC_ENABL BK1 1 io IO2 BK2 1 io C2 BL1 1 io DATA_ENABL BL2 1 io IO_ENABL BM1 1 io IO3 BM2 1 io DATA2 BN1 1 io SC3 BN2 1 io MQ3_H BP1 1 io MA_ENABL BP2 1 io DATA3 BR1 1 io MEM2 BR2 1 io BR2 BS1 1 io DA2 BS2 1 io PC_ENABL BT1 1 io GND BT2 1 io DA_ENABL BU1 1 io BU1 BU2 1 io MEM_ENABL BV1 1 io BV1 BV2 1 io BV2