// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// c5: c_us 
// c6: c_us 
// c7: c_us 
// c8: c_us 
// c9: c_us 
// c10: c_us 
// c11: c_us 
// c12: c_us 
// c13: c_us 
// c14: c_us 
// c15: c_us 
// c16: c_us 
// c17: c_us 
// e1: sn7453 
// bb2 = !(ad2 & rwb3_h
//       # af1
//       # ae2 & ae1
//       # ac1 & ab2); 
// n_t_3x = !bb2; 
// e2: sn7453 
// bb2 = !(tmasu3 & ap1
//       # al2 & tac3_h
//       # al1 & af2
//       # tma3 & as2); 
// n_t_3x = !bb2; 
// e3: sn7474 
module m222x (ab2, ac1, ad2, ae1, ae2, af1, af2, al1, al2, am1, am2, an2, ap1, ap2, ar2, as1, as2, av1, bb1, bb2, bc1, be1, bf1, bh1, bh2, bj1, bj2, bk1, bk2, bl1, bl2, bm1, bm2, bn1, bn2, bp2, br1, bs1, bu1, carry_in_l, carry_out_l, load_rwb, load_tac, load_tb, load_tbn, load_tma, load_tmasu, n3v3, phase, rwb3_h, rwb_out, shift_rwb, tac2_h, tac2_l, tac3_h, tac3_l, tape_bus2, tape_bus3, tb2_h, tb3_h, tbn2, tbn3, tma2, tma3, tmasu2, tmasu3);
input ab2;
input ac1;
input ad2;
input ae1;
input ae2;
input af1;
input af2;
input al1;
input al2;
input am1;
input am2;
inout an2;
input ap1;
input ap2;
input ar2;
input as1;
input as2;
input av1;
inout bb1;
inout bb2;
input bc1;
input be1;
input bf1;
input bh1;
output bh2;
output bj1;
input bj2;
input bk1;
input bk2;
input bl1;
input bl2;
input bm1;
input bm2;
inout bn1;
input bn2;
input bp2;
input br1;
input bs1;
input bu1;
input carry_in_l;
output carry_out_l;
input load_rwb;
input load_tac;
input load_tb;
input load_tbn;
input load_tma;
input load_tmasu;
input n3v3;
output phase;
inout reg rwb3_h;
output rwb_out;
input shift_rwb;
inout reg tac2_h;
output tac2_l;
inout reg tac3_h;
output tac3_l;
inout tape_bus2;
inout tape_bus3;
inout reg tb2_h;
inout reg tb3_h;
output reg tbn2;
output reg tbn3;
inout reg tma2;
inout reg tma3;
inout reg tmasu2;
inout reg tmasu3;

reg rwb2_h_m;
reg rwb3_h_m;
reg tac2_h_m;
reg tac3_h_m;
reg tb2_h_m;
reg tb3_h_m;
reg tbn2_m;
reg tbn3_m;
reg tma2_m;
reg tma3_m;
reg tmasu2_m;
reg tmasu3_m;

reg rwb2_h;
wire n_t_16x;
wire n_t_17x;
wire n_t_7x;
wire n_t_8x;
always @(load_tmasu, n3v3, n3v3, tape_bus3)
  if (~n3v3) begin
    tmasu3_m <= 1'b0;
  end else
  if (~n3v3) begin
    tmasu3_m <= 1'b1;
  end else
  if (~(load_tmasu)) begin
    tmasu3_m <= tape_bus3;
  end
always @(load_tmasu, n3v3, n3v3, tmasu3_m)
  if (~n3v3) begin
    tmasu3 <= 1'b0;
  end else
  if (~n3v3) begin
    tmasu3 <= 1'b1;
  end else
  if (load_tmasu) begin
    tmasu3 <= tmasu3_m;
  end
always @(load_tma, n3v3, n3v3, tape_bus3)
  if (~n3v3) begin
    tma3_m <= 1'b0;
  end else
  if (~n3v3) begin
    tma3_m <= 1'b1;
  end else
  if (~(load_tma)) begin
    tma3_m <= tape_bus3;
  end
always @(load_tma, n3v3, n3v3, tma3_m)
  if (~n3v3) begin
    tma3 <= 1'b0;
  end else
  if (~n3v3) begin
    tma3 <= 1'b1;
  end else
  if (load_tma) begin
    tma3 <= tma3_m;
  end
// e4: sn7474 
always @(load_tac, n3v3, n3v3, tape_bus2)
  if (~n3v3) begin
    tac2_h_m <= 1'b0;
  end else
  if (~n3v3) begin
    tac2_h_m <= 1'b1;
  end else
  if (~(load_tac)) begin
    tac2_h_m <= tape_bus2;
  end
always @(load_tac, n3v3, n3v3, tac2_h_m)
  if (~n3v3) begin
    tac2_h <= 1'b0;
  end else
  if (~n3v3) begin
    tac2_h <= 1'b1;
  end else
  if (load_tac) begin
    tac2_h <= tac2_h_m;
  end
assign tac2_l = ~tac2_h;
always @(load_tac, n3v3, n3v3, tape_bus3)
  if (~n3v3) begin
    tac3_h_m <= 1'b0;
  end else
  if (~n3v3) begin
    tac3_h_m <= 1'b1;
  end else
  if (~(load_tac)) begin
    tac3_h_m <= tape_bus3;
  end
always @(load_tac, n3v3, n3v3, tac3_h_m)
  if (~n3v3) begin
    tac3_h <= 1'b0;
  end else
  if (~n3v3) begin
    tac3_h <= 1'b1;
  end else
  if (load_tac) begin
    tac3_h <= tac3_h_m;
  end
assign tac3_l = ~tac3_h;
// e5: sn7453 
// an2 = !(rwb2_h & ad2
//       # ap2
//       # ar2 & as1
//       # am2 & ae2); 
// n_t_6x = !an2; 
// e6: sn7453 
// an2 = !(tac2_h & al2
//       # ap1 & tmasu2
//       # tma2 & as2
//       # am1 & al1); 
// n_t_6x = !an2; 
// e7: sn7474 
always @(load_tma, n3v3, n3v3, tape_bus2)
  if (~n3v3) begin
    tma2_m <= 1'b0;
  end else
  if (~n3v3) begin
    tma2_m <= 1'b1;
  end else
  if (~(load_tma)) begin
    tma2_m <= tape_bus2;
  end
always @(load_tma, n3v3, n3v3, tma2_m)
  if (~n3v3) begin
    tma2 <= 1'b0;
  end else
  if (~n3v3) begin
    tma2 <= 1'b1;
  end else
  if (load_tma) begin
    tma2 <= tma2_m;
  end
always @(load_tmasu, n3v3, n3v3, tape_bus2)
  if (~n3v3) begin
    tmasu2_m <= 1'b0;
  end else
  if (~n3v3) begin
    tmasu2_m <= 1'b1;
  end else
  if (~(load_tmasu)) begin
    tmasu2_m <= tape_bus2;
  end
always @(load_tmasu, n3v3, n3v3, tmasu2_m)
  if (~n3v3) begin
    tmasu2 <= 1'b0;
  end else
  if (~n3v3) begin
    tmasu2 <= 1'b1;
  end else
  if (load_tmasu) begin
    tmasu2 <= tmasu2_m;
  end
// e8: sn7474 
always @(load_tbn, n3v3, n3v3, tape_bus2)
  if (~n3v3) begin
    tbn2_m <= 1'b0;
  end else
  if (~n3v3) begin
    tbn2_m <= 1'b1;
  end else
  if (~(load_tbn)) begin
    tbn2_m <= tape_bus2;
  end
always @(load_tbn, n3v3, n3v3, tbn2_m)
  if (~n3v3) begin
    tbn2 <= 1'b0;
  end else
  if (~n3v3) begin
    tbn2 <= 1'b1;
  end else
  if (load_tbn) begin
    tbn2 <= tbn2_m;
  end
always @(load_tbn, n3v3, n3v3, tape_bus3)
  if (~n3v3) begin
    tbn3_m <= 1'b0;
  end else
  if (~n3v3) begin
    tbn3_m <= 1'b1;
  end else
  if (~(load_tbn)) begin
    tbn3_m <= tape_bus3;
  end
always @(load_tbn, n3v3, n3v3, tbn3_m)
  if (~n3v3) begin
    tbn3 <= 1'b0;
  end else
  if (~n3v3) begin
    tbn3 <= 1'b1;
  end else
  if (load_tbn) begin
    tbn3 <= tbn3_m;
  end
// e9: sn7482 
assign tape_bus3 = ~(carry_in_l
                      ^ bb2
                      ^ bb1);
assign gdollar_0 = carry_in_l & bb2
                    | bb2 & bb1
                    | carry_in_l & bb1;
assign tape_bus2 = ~(an2
                      ^ bn1
                      ^ gdollar_0);
assign carry_out_l = gdollar_0 & an2
                      | an2 & bn1
                      | bn1 & gdollar_0;
// e10: sn7474 
always @(shift_rwb, n_t_17x, n_t_16x, rwb3_h)
  if (~n_t_17x) begin
    rwb2_h_m <= 1'b0;
  end else
  if (~n_t_16x) begin
    rwb2_h_m <= 1'b1;
  end else
  if (~(shift_rwb)) begin
    rwb2_h_m <= rwb3_h;
  end
always @(shift_rwb, n_t_17x, n_t_16x, rwb2_h_m)
  if (~n_t_17x) begin
    rwb2_h <= 1'b0;
  end else
  if (~n_t_16x) begin
    rwb2_h <= 1'b1;
  end else
  if (shift_rwb) begin
    rwb2_h <= rwb2_h_m;
  end
always @(shift_rwb, n_t_7x, n_t_8x, av1)
  if (~n_t_7x) begin
    rwb3_h_m <= 1'b0;
  end else
  if (~n_t_8x) begin
    rwb3_h_m <= 1'b1;
  end else
  if (~(shift_rwb)) begin
    rwb3_h_m <= av1;
  end
always @(shift_rwb, n_t_7x, n_t_8x, rwb3_h_m)
  if (~n_t_7x) begin
    rwb3_h <= 1'b0;
  end else
  if (~n_t_8x) begin
    rwb3_h <= 1'b1;
  end else
  if (shift_rwb) begin
    rwb3_h <= rwb3_h_m;
  end
// e11: sn7400 
assign n_t_16x = ~(tb2_h & load_rwb);
assign n_t_17x = ~(~tb2_h & load_rwb);
assign n_t_8x = ~(tb3_h & load_rwb);
assign n_t_7x = ~(~tb3_h & load_rwb);
// e12: sn7474 
always @(load_tb, n3v3, n3v3, tape_bus2)
  if (~n3v3) begin
    tb2_h_m <= 1'b0;
  end else
  if (~n3v3) begin
    tb2_h_m <= 1'b1;
  end else
  if (~(load_tb)) begin
    tb2_h_m <= tape_bus2;
  end
always @(load_tb, n3v3, n3v3, tb2_h_m)
  if (~n3v3) begin
    tb2_h <= 1'b0;
  end else
  if (~n3v3) begin
    tb2_h <= 1'b1;
  end else
  if (load_tb) begin
    tb2_h <= tb2_h_m;
  end
always @(load_tb, n3v3, n3v3, tape_bus3)
  if (~n3v3) begin
    tb3_h_m <= 1'b0;
  end else
  if (~n3v3) begin
    tb3_h_m <= 1'b1;
  end else
  if (~(load_tb)) begin
    tb3_h_m <= tape_bus3;
  end
always @(load_tb, n3v3, n3v3, tb3_h_m)
  if (~n3v3) begin
    tb3_h <= 1'b0;
  end else
  if (~n3v3) begin
    tb3_h <= 1'b1;
  end else
  if (load_tb) begin
    tb3_h <= tb3_h_m;
  end
// e13: sn7453 
// bb1 = !(bk1 & tb3_h
//        # be1 & bl1
//        # bh1 & bf1
//        # bc1 & bs1); 
// !bb1 = !bb1; 
// e14: sn7450 
// e15: sn7400 
// e16: sn7453 
// bn1 = !(tb2_h & bk1
//        # bf1 & br1
//        # bs1 & bj2
//        # bm1 & bl1); 
// n_t_9x = !bn1; 
// e17: sn7453 
// bn1 = !(bp2 & bu1
//        # bn2 & bm2
//        # bk2 & bl2); 
// n_t_9x = !bn1; 
// open collector 'wire-or's 
assign bn1 = ~((tb2_h & bk1
                 | bf1 & br1
                 | bs1 & bj2
                 | bm1 & bl1)
                | (bp2 & bu1
                   | bn2 & bm2
                   | bk2 & bl2));
assign bb1 = ~((bk1 & tb3_h
                 | be1 & bl1
                 | bh1 & bf1
                 | bc1 & bs1));
assign n_t_3x = ~bb2;
assign bb2 = ~((ad2 & rwb3_h
                 | af1
                 | ae2 & ae1
                 | ac1 & ab2)
                | (tmasu3 & ap1
                   | al2 & tac3_h
                   | al1 & af2
                   | tma3 & as2));
assign an2 = ~((rwb2_h & ad2
                 | ap2
                 | ar2 & as1
                 | am2 & ae2)
                | (tac2_h & al2
                   | ap1 & tmasu2
                   | tma2 & as2
                   | am1 & al1));
assign n_t_6x = ~an2;
assign n_t_9x = ~bn1;
endmodule