// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// c5: c_us 
// c6: c_us 
// c7: c_us 
// e1: sn74h50 
module m223x (n_t_10x, n_t_11x, n_t_12x, n_t_13x, n_t_16x, n_t_17x, n_t_18x, n_t_19x, n_t_20x, n_t_21x, n_t_22x, n_t_23x, n_t_24x, n_t_25x, n_t_26x, n_t_27x, n_t_28x, n_t_29x, n_t_30x, n_t_31x, n_t_33x, n_t_34x, n_t_36x, n_t_3x, n_t_4x, n_t_5x, n_t_6x, n_t_7x, n_t_8x, n_t_9x);
input n_t_10x;
input n_t_11x;
input n_t_12x;
input n_t_13x;
inout n_t_16x;
inout n_t_17x;
inout n_t_18x;
output reg n_t_19x;
output reg n_t_20x;
output reg n_t_21x;
output reg n_t_22x;
input n_t_23x;
input n_t_24x;
input n_t_25x;
input n_t_26x;
input n_t_27x;
input n_t_28x;
input n_t_29x;
input n_t_30x;
inout n_t_31x;
inout n_t_33x;
inout n_t_34x;
inout n_t_36x;
inout n_t_3x;
input n_t_4x;
input n_t_5x;
input n_t_6x;
input n_t_7x;
input n_t_8x;
input n_t_9x;

reg n_t_19x_m;
reg n_t_20x_m;
reg n_t_21x_m;
reg n_t_22x_m;

wire n_t_14x;
wire n_t_15x;
wire n_t_1x;
wire n_t_2x;
assign n_t_2x = ~(n_t_4x & n_t_6x
                   | n_t_5x & n_t_7x);
assign n_t_1x = ~(n_t_6x & n_t_8x
                   | n_t_7x & n_t_9x);
// e2: sn7474 
always @(n_t_23x, n_t_28x, n_t_24x, n_t_1x)
  if (~n_t_28x) begin
    n_t_20x_m <= 1'b0;
  end else
  if (~n_t_24x) begin
    n_t_20x_m <= 1'b1;
  end else
  if (~(n_t_23x)) begin
    n_t_20x_m <= ~n_t_1x;
  end
always @(n_t_23x, n_t_28x, n_t_24x, n_t_20x_m)
  if (~n_t_28x) begin
    n_t_20x <= 1'b0;
  end else
  if (~n_t_24x) begin
    n_t_20x <= 1'b1;
  end else
  if (n_t_23x) begin
    n_t_20x <= n_t_20x_m;
  end
always @(n_t_23x, n_t_25x, n_t_24x, n_t_2x)
  if (~n_t_25x) begin
    n_t_19x_m <= 1'b0;
  end else
  if (~n_t_24x) begin
    n_t_19x_m <= 1'b1;
  end else
  if (~(n_t_23x)) begin
    n_t_19x_m <= ~n_t_2x;
  end
always @(n_t_23x, n_t_25x, n_t_24x, n_t_19x_m)
  if (~n_t_25x) begin
    n_t_19x <= 1'b0;
  end else
  if (~n_t_24x) begin
    n_t_19x <= 1'b1;
  end else
  if (n_t_23x) begin
    n_t_19x <= n_t_19x_m;
  end
// e3: sn74h50 
assign n_t_3x = ~(n_t_31x & n_t_29x
                   | n_t_15x & n_t_30x);
assign n_t_16x = ~(n_t_33x & n_t_29x
                    | n_t_30x & n_t_14x);
// e4: sn74h50 
assign n_t_14x = ~(n_t_10x & n_t_6x
                    | n_t_12x & n_t_7x);
assign n_t_15x = ~(n_t_6x & n_t_11x
                    | n_t_7x & n_t_13x);
// e5: sn7474 
always @(n_t_23x, n_t_26x, n_t_24x, n_t_15x)
  if (~n_t_26x) begin
    n_t_22x_m <= 1'b0;
  end else
  if (~n_t_24x) begin
    n_t_22x_m <= 1'b1;
  end else
  if (~(n_t_23x)) begin
    n_t_22x_m <= ~n_t_15x;
  end
always @(n_t_23x, n_t_26x, n_t_24x, n_t_22x_m)
  if (~n_t_26x) begin
    n_t_22x <= 1'b0;
  end else
  if (~n_t_24x) begin
    n_t_22x <= 1'b1;
  end else
  if (n_t_23x) begin
    n_t_22x <= n_t_22x_m;
  end
always @(n_t_23x, n_t_27x, n_t_24x, n_t_14x)
  if (~n_t_27x) begin
    n_t_21x_m <= 1'b0;
  end else
  if (~n_t_24x) begin
    n_t_21x_m <= 1'b1;
  end else
  if (~(n_t_23x)) begin
    n_t_21x_m <= ~n_t_14x;
  end
always @(n_t_23x, n_t_27x, n_t_24x, n_t_21x_m)
  if (~n_t_27x) begin
    n_t_21x <= 1'b0;
  end else
  if (~n_t_24x) begin
    n_t_21x <= 1'b1;
  end else
  if (n_t_23x) begin
    n_t_21x <= n_t_21x_m;
  end
// e6: sn74h50 
assign n_t_17x = ~(n_t_34x & n_t_29x
                    | n_t_1x & n_t_30x);
assign n_t_18x = ~(n_t_36x & n_t_29x
                    | n_t_30x & n_t_2x);
// e7: sn74h00 
assign n_t_31x = ~(n_t_3x & );
assign n_t_33x = ~(n_t_16x & );
assign n_t_36x = ~(n_t_18x & );
assign n_t_34x = ~(n_t_17x & );
// open collector 'wire-or's 
endmodule