// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// c5: c_us 
// c6: c_us 
// c7: c_us 
// c8: c_us 
// c9: c_us 
// c10: c_us 
// c11: c_us 
// c12: c_us 
// c13: c_us 
// c14: c_us 
// c15: c_us 
// c16: c_us 
// c17: c_us 
// c18: c_us 
// c19: c_us 
// c20: c_us 
// c21: c_us 
// c22: c_us 
// c23: c_us 
// c24: cpol_use 
// c25: c_us 
// c26: c_us 
// c27: c_us 
// e1: sn74h62 
// n_t_5x = !(ae2 & af2
//       # ae1 & n3v3 & ad1
//       # aa1 & ad2 & ad2
//       # af1 & ab1); 
// aj2 = !n_t_5x; 
// e2: sn74h53 
// ar2 = !(bt2 & ah2
//       # af2 & am2
//       # ac1 & ad1 & n3v3
//       # ad2 & bu2); 
// n_t_3x = !ar2; 
// e3: sn74h62 
// n_t_3x = !(af1 & bv1
//       # n3v3 & am1 & as1
//       # ah1 & aa1 & aa1
//       # aj1 & at2); 
// ar2 = !n_t_3x; 
// e4: sn74h53 
// aj2 = !(an2 & aj1
//       # al1 & am2
//       # al2 & am1 & n3v3
//       # ah1 & ah2); 
// n_t_5x = !aj2; 
// e5: sn74h53 
// av1 = !(bt2 & aa1
//       # af2 & af1
//       # ad1 & ak1 & n3v3
//       # ad2 & bh1); 
// n_t_1x = !av1; 
// e6: sn74h62 
// n_t_1x = !(ah2 & bv1
//       # n3v3 & am1 & an2
//       # ah1 & bu2 & bu2
//       # aj1 & av2); 
// av1 = !n_t_1x; 
// e7: sn7474 
module m227x (n3v3, aa1, ab1, ac1, ad1, ad2, ae1, ae2, af1, af2, ah1, ah2, aj1, aj2, ak1, al1, al2, am1, am2, an1, an2, ap1, ap2, ar1, ar2, as1, as2, at2, au1, au2, av1, av2, ba1, bb1, bc1, bd1, bd2, be1, be2, bf1, bf2, bh1, bh2, bj1, bj2, bk1, bk2, bl1, bl2, bm1, bm2, bn1, bn2, bp1, bp2, br1, br2, bs1, bs2, bt2, bu1, bu2, bv1, bv2);
input n3v3;
input aa1;
input ab1;
input ac1;
input ad1;
input ad2;
input ae1;
input ae2;
input af1;
input af2;
input ah1;
input ah2;
input aj1;
inout aj2;
input ak1;
input al1;
input al2;
input am1;
input am2;
input an1;
inout an2;
input ap1;
inout reg ap2;
inout reg ar1;
inout ar2;
inout as1;
inout reg as2;
inout at2;
input au1;
inout reg au2;
inout av1;
inout av2;
input ba1;
input bb1;
inout bc1;
inout bd1;
inout bd2;
input be1;
inout be2;
input bf1;
inout reg bf2;
input bh1;
inout bh2;
input bj1;
inout reg bj2;
inout bk1;
inout bk2;
input bl1;
inout reg bl2;
inout bm1;
inout reg bm2;
input bn1;
inout bn2;
input bp1;
inout reg bp2;
input br1;
inout br2;
input bs1;
inout bs2;
input bt2;
input bu1;
input bu2;
input bv1;
input bv2;

reg ap2_m;
reg ar1_m;
reg as2_m;
reg au2_m;
reg bf2_m;
reg bj2_m;
reg bl2_m;
reg bm2_m;
reg bp2_m;

always @(an1, n3v3, n3v3, aj2)
  if (~n3v3) begin
    ar1_m <= 1'b0;
  end else
  if (~n3v3) begin
    ar1_m <= 1'b1;
  end else
  if (~(an1)) begin
    ar1_m <= aj2;
  end
always @(an1, n3v3, n3v3, ar1_m)
  if (~n3v3) begin
    ar1 <= 1'b0;
  end else
  if (~n3v3) begin
    ar1 <= 1'b1;
  end else
  if (an1) begin
    ar1 <= ar1_m;
  end
assign as1 = ~ar1;
always @(an1, n3v3, n3v3, ar2)
  if (~n3v3) begin
    ap2_m <= 1'b0;
  end else
  if (~n3v3) begin
    ap2_m <= 1'b1;
  end else
  if (~(an1)) begin
    ap2_m <= ar2;
  end
always @(an1, n3v3, n3v3, ap2_m)
  if (~n3v3) begin
    ap2 <= 1'b0;
  end else
  if (~n3v3) begin
    ap2 <= 1'b1;
  end else
  if (an1) begin
    ap2 <= ap2_m;
  end
assign an2 = ~ap2;
// e8: sn74h53 
// bd2 = !(bt2 & bu2
//        # af2 & ah2
//        # ad1 & n3v3 & au1
//        # ad2 & bb1); 
// n_t_20x = !bd2; 
// e9: sn74h62 
// n_t_20x = !(aa1 & bv1
//        # n3v3 & am1 & at2
//        # bh1 & ah1 & ah1
//        # aj1 & bh2); 
// bd2 = !n_t_20x; 
// e10: sn74h53 
// bd1 = !(bt2 & bh1
//        # af2 & aa1
//        # ad1 & ba1 & n3v3
//        # ad2 & be1); 
// n_t_18x = !bd1; 
// e11: sn74h62 
// n_t_18x = !(bu2 & bv1
//        # n3v3 & am1 & av2
//        # ah1 & bb1 & bb1
//        # aj1 & be2); 
// bd1 = !n_t_18x; 
// e12: sn7474 
always @(an1, n3v3, n3v3, bd2)
  if (~n3v3) begin
    au2_m <= 1'b0;
  end else
  if (~n3v3) begin
    au2_m <= 1'b1;
  end else
  if (~(an1)) begin
    au2_m <= bd2;
  end
always @(an1, n3v3, n3v3, au2_m)
  if (~n3v3) begin
    au2 <= 1'b0;
  end else
  if (~n3v3) begin
    au2 <= 1'b1;
  end else
  if (an1) begin
    au2 <= au2_m;
  end
assign av2 = ~au2;
always @(an1, n3v3, n3v3, av1)
  if (~n3v3) begin
    as2_m <= 1'b0;
  end else
  if (~n3v3) begin
    as2_m <= 1'b1;
  end else
  if (~(an1)) begin
    as2_m <= av1;
  end
always @(an1, n3v3, n3v3, as2_m)
  if (~n3v3) begin
    as2 <= 1'b0;
  end else
  if (~n3v3) begin
    as2 <= 1'b1;
  end else
  if (an1) begin
    as2 <= as2_m;
  end
assign at2 = ~as2;
// e13: sn74h53 
// bc1 = !(bt2 & bb1
//        # af2 & bu2
//        # ad1 & bf1 & n3v3
//        # ad2 & bu1); 
// n_t_16x = !bc1; 
// e14: sn74h62 
// n_t_16x = !(bh1 & bv1
//        # n3v3 & am1 & bh2
//        # ah1 & be1 & be1
//        # aj1 & bk2); 
// bc1 = !n_t_16x; 
// e15: sn7474 
always @(an1, n3v3, n3v3, bd1)
  if (~n3v3) begin
    bj2_m <= 1'b0;
  end else
  if (~n3v3) begin
    bj2_m <= 1'b1;
  end else
  if (~(an1)) begin
    bj2_m <= bd1;
  end
always @(an1, n3v3, n3v3, bj2_m)
  if (~n3v3) begin
    bj2 <= 1'b0;
  end else
  if (~n3v3) begin
    bj2 <= 1'b1;
  end else
  if (an1) begin
    bj2 <= bj2_m;
  end
assign bh2 = ~bj2;
always @(an1, n3v3, n3v3, bc1)
  if (~n3v3) begin
    bf2_m <= 1'b0;
  end else
  if (~n3v3) begin
    bf2_m <= 1'b1;
  end else
  if (~(an1)) begin
    bf2_m <= bc1;
  end
always @(an1, n3v3, n3v3, bf2_m)
  if (~n3v3) begin
    bf2 <= 1'b0;
  end else
  if (~n3v3) begin
    bf2 <= 1'b1;
  end else
  if (an1) begin
    bf2 <= bf2_m;
  end
assign be2 = ~bf2;
// e16: sn74h53 
// bk1 = !(bt2 & be1
//        # af2 & bh1
//        # ad1 & bj1 & n3v3
//        # ad2 & bn1); 
// n_t_23x = !bk1; 
// e17: sn74h62 
// n_t_23x = !(bb1 & bv1
//        # n3v3 & am1 & be2
//        # ah1 & bu1 & bu1
//        # aj1 & bn2); 
// bk1 = !n_t_23x; 
// e18: sn7474 
always @(an1, n3v3, n3v3, bm1)
  if (~n3v3) begin
    bm2_m <= 1'b0;
  end else
  if (~n3v3) begin
    bm2_m <= 1'b1;
  end else
  if (~(an1)) begin
    bm2_m <= bm1;
  end
always @(an1, n3v3, n3v3, bm2_m)
  if (~n3v3) begin
    bm2 <= 1'b0;
  end else
  if (~n3v3) begin
    bm2 <= 1'b1;
  end else
  if (an1) begin
    bm2 <= bm2_m;
  end
assign bn2 = ~bm2;
always @(an1, n3v3, n3v3, bk1)
  if (~n3v3) begin
    bl2_m <= 1'b0;
  end else
  if (~n3v3) begin
    bl2_m <= 1'b1;
  end else
  if (~(an1)) begin
    bl2_m <= bk1;
  end
always @(an1, n3v3, n3v3, bl2_m)
  if (~n3v3) begin
    bl2 <= 1'b0;
  end else
  if (~n3v3) begin
    bl2 <= 1'b1;
  end else
  if (an1) begin
    bl2 <= bl2_m;
  end
assign bk2 = ~bl2;
// e19: sn74h53 
// bm1 = !(bt2 & bu1
//        # af2 & bb1
//        # ad1 & bp1 & n3v3
//        # ad2 & bl1); 
// n_t_24x = !bm1; 
// e20: sn74h62 
// n_t_24x = !(be1 & bv1
//        # n3v3 & am1 & bk2
//        # ah1 & bn1 & bn1
//        # aj1 & br2); 
// bm1 = !n_t_24x; 
// e21: sn7474 
always @(an1, n3v3, n3v3, bs2)
  if (~n3v3) begin
    bp2_m <= 1'b0;
  end else
  if (~n3v3) begin
    bp2_m <= 1'b1;
  end else
  if (~(an1)) begin
    bp2_m <= bs2;
  end
always @(an1, n3v3, n3v3, bp2_m)
  if (~n3v3) begin
    bp2 <= 1'b0;
  end else
  if (~n3v3) begin
    bp2 <= 1'b1;
  end else
  if (an1) begin
    bp2 <= bp2_m;
  end
assign br2 = ~bp2;
// e22: sn74h53 
// bs2 = !(bt2 & bn1
//        # af2 & be1
//        # ad1 & bs1 & n3v3
//        # ad2 & br1); 
// n_t_14x = !bs2; 
// e23: sn74h62 
// n_t_14x = !(bu1 & bv1
//        # n3v3 & am1 & bn2
//        # ah1 & ap1 & ap1
//        # aj1 & bv2); 
// bs2 = !n_t_14x; 
// open collector 'wire-or's 
assign n_t_14x = ~(bs2
                    | (bu1 & bv1
                       | n3v3 & am1 & bn2
                       | ah1 & ap1 & ap1
                       | aj1 & bv2));
assign n_t_16x = ~(bc1
                    | (bh1 & bv1
                       | n3v3 & am1 & bh2
                       | ah1 & be1 & be1
                       | aj1 & bk2));
assign bc1 = ~((bt2 & bb1
                 | af2 & bu2
                 | ad1 & bf1 & n3v3
                 | ad2 & bu1)
                | n_t_16x);
assign n_t_18x = ~(bd1
                    | (bu2 & bv1
                       | n3v3 & am1 & av2
                       | ah1 & bb1 & bb1
                       | aj1 & be2));
assign bd1 = ~((bt2 & bh1
                 | af2 & aa1
                 | ad1 & ba1 & n3v3
                 | ad2 & be1)
                | n_t_18x);
assign n_t_1x = ~(av1
                   | (ah2 & bv1
                      | n3v3 & am1 & an2
                      | ah1 & bu2 & bu2
                      | aj1 & av2));
assign n_t_20x = ~(bd2
                    | (aa1 & bv1
                       | n3v3 & am1 & at2
                       | bh1 & ah1 & ah1
                       | aj1 & bh2));
assign bd2 = ~((bt2 & bu2
                 | af2 & ah2
                 | ad1 & n3v3 & au1
                 | ad2 & bb1)
                | n_t_20x);
assign bk1 = ~((bt2 & be1
                 | af2 & bh1
                 | ad1 & bj1 & n3v3
                 | ad2 & bn1)
                | n_t_23x);
assign n_t_23x = ~(bk1
                    | (bb1 & bv1
                       | n3v3 & am1 & be2
                       | ah1 & bu1 & bu1
                       | aj1 & bn2));
assign n_t_24x = ~(bm1
                    | (be1 & bv1
                       | n3v3 & am1 & bk2
                       | ah1 & bn1 & bn1
                       | aj1 & br2));
assign bm1 = ~((bt2 & bu1
                 | af2 & bb1
                 | ad1 & bp1 & n3v3
                 | ad2 & bl1)
                | n_t_24x);
assign bs2 = ~((bt2 & bn1
                 | af2 & be1
                 | ad1 & bs1 & n3v3
                 | ad2 & br1)
                | n_t_14x);
assign av1 = ~((bt2 & aa1
                 | af2 & af1
                 | ad1 & ak1 & n3v3
                 | ad2 & bh1)
                | n_t_1x);
assign n_t_3x = ~(ar2
                   | (af1 & bv1
                      | n3v3 & am1 & as1
                      | ah1 & aa1 & aa1
                      | aj1 & at2));
assign ar2 = ~((bt2 & ah2
                 | af2 & am2
                 | ac1 & ad1 & n3v3
                 | ad2 & bu2)
                | n_t_3x);
assign n_t_5x = ~((ae2 & af2
                    | ae1 & n3v3 & ad1
                    | aa1 & ad2 & ad2
                    | af1 & ab1)
                   | aj2);
assign aj2 = ~(n_t_5x
                | (an2 & aj1
                   | al1 & am2
                   | al2 & am1 & n3v3
                   | ah1 & ah2));
endmodule