Exported from /home/vrs/Eagle/projects/DEC/Mxxx/M228/M228X.sch Part Pad Pin Dir Net C1 1 1 pas VCC 2 2 pas GND C2 1 1 pas VCC 2 2 pas GND C3 1 1 pas VCC 2 2 pas GND C4 1 1 pas VCC 2 2 pas GND C5 1 1 pas VCC 2 2 pas GND C6 1 1 pas VCC 2 2 pas GND C7 1 1 pas VCC 2 2 pas GND C8 1 1 pas VCC 2 2 pas GND C9 1 1 pas VCC 2 2 pas GND C10 1 1 pas VCC 2 2 pas GND C11 1 1 pas VCC 2 2 pas GND C12 1 1 pas VCC 2 2 pas GND C13 1 1 pas VCC 2 2 pas GND C14 1 1 pas VCC 2 2 pas GND C15 1 1 pas VCC 2 2 pas GND C16 1 1 pas VCC 2 2 pas GND C17 1 1 pas VCC 2 2 pas GND C18 1 1 pas VCC 2 2 pas GND C19 1 1 pas VCC 2 2 pas GND C20 1 1 pas VCC 2 2 pas GND C21 1 1 pas VCC 2 2 pas GND C22 1 1 pas +3V@R3 2 2 pas GND C23 1 1 pas +3V@R1 2 2 pas GND C24 1 1 pas VCC 2 2 pas GND C26 + + pas VCC - - pas GND E1 1 I0 in !MK_DATA_SYNC 2 I1 in !MK_DATA_SYNC 3 O out MK_DATA_SYNC 4 I0 in !MK_BLK_START 5 I1 in !MK_BLK_START 6 O out MK_BLK_START 8 O out MK_END 9 I0 in !MK_END 10 I1 in !MK_END 11 O out MK_BLK_MK 12 I0 in !MK_BLK_MK 13 I1 in !MK_BLK_MK E2 1 I0 in W1*W5 2 I1 in W3 3 I2 in W7 4 I3 in !W2 5 I4 in !W9 6 I5 in W8 8 O out !MK_BLK_MK 11 I6 in !W6 12 I7 in !W4 E3 1 I0 in !W3 2 I1 in !W6 3 I2 in !W4 4 I3 in !W7 5 I4 in W8 6 I5 in !W9 8 O out !MK_END 11 I6 in W1*W5 12 I7 in W2 E4 1 O out AU1 2 I0 in W8 3 I1 in !W9 4 O out SH_ST_OUT 5 I0 in N$3 6 I1 in !TP0 8 I0 in !W5 9 I1 in !W1 10 O out W1*W5 E5 1 CLR in !0_TO_STATE 2 D in W7 3 CLK in TP1 4 PRE in +3V@R1 5 Q out W6 6 !Q out !W6 8 !Q out !W7 9 Q out W7 10 PRE in +3V@R1 11 CLK in TP1 12 D in W8 13 CLR in !0_TO_STATE E6 1 I0 in !W3 2 I1 in !W4 3 I2 in W6 4 I3 in !W7 5 I4 in W8 6 I5 in !W9 8 O out !MK_DATA_SYNC 11 I6 in W1*W5 12 I7 in W2 E7 1 I4 in MK_BLK_START 8 O out N$3 9 I2 in SHIFT_I 10 I1 in ST_IDLE 11 I6 pas N$2 12 I5 pas N$1 13 I3 in ST_BLK_MK E8 1 CLR in !0_TO_W 2 D in AS2 3 CLK in TP1 4 PRE in +3V@R1 5 Q out W9 6 !Q out !W9 8 !Q out !W4 9 Q out W4 10 PRE in +3V@R1 11 CLK in TP1 12 D in W5 13 CLR in !0_TO_STATE E9 1 I0 in !W3 2 I1 in !W8 3 I2 in W6 4 I3 in !W7 5 I4 in !W5 6 I5 in !W9 8 O out !MK_BLK_START 11 I6 in !W4 12 I7 in W1 E10 1 CLR in !0_TO_STATE 2 D in ST_IDLE_IN 3 CLK in SH_ST 4 PRE in +3V@R3 5 Q out ST_BLK_MK 9 Q out ST_IDLE 10 PRE in !0_TO_STATE 11 CLK in SH_ST 12 D in ST_CK 13 CLR in +3V@R3 E11 1 CLR in !0_TO_W 2 D in W9 3 CLK in TP1 4 PRE in +3V@R1 5 Q out W8 6 !Q out !W8 E12 1 I0 in !W3 2 I1 in !W8 3 I2 in !W2 4 I3 in !W7 5 I4 in !W9 6 I5 in W1*W5 8 O out !MK_DATA 11 I6 in W4 12 I7 in W6 E13 1 CLR in !0_TO_STATE 2 D in ST_REV_CK 3 CLK in SH_ST 4 PRE in +3V@R3 5 Q out DATA 9 Q out ST_REV_CK 10 PRE in +3V@R3 11 CLK in SH_ST 12 D in ST_BLK_MK 13 CLR in !0_TO_STATE E14 1 CLR in !0_TO_W 2 D in W3 3 CLK in TP1 4 PRE in +3V@R1 5 Q out W2 6 !Q out !W2 8 !Q out !W3 9 Q out W3 10 PRE in +3V@R1 11 CLK in TP1 12 D in W4 13 CLR in !0_TO_W E15 1 I0 in BH1 2 I1 in W3 3 I2 in !W6 4 I3 in W9 5 I4 in W7 6 I5 in W1*W5 8 O out !SYNC 11 I6 in !W8 12 I7 in !W4 E16 1 CLR in !0_TO_STATE 2 D in ST_FINAL 3 CLK in SH_ST 4 PRE in +3V@R3 5 Q out ST_CK 9 Q out ST_FINAL 10 PRE in +3V@R3 11 CLK in SH_ST 12 D in DATA 13 CLR in !0_TO_STATE E17 1 CLR in !0_TO_W 2 D in W6 3 CLK in TP1 4 PRE in +3V@R1 5 Q out W5 6 !Q out !W5 8 !Q out !W1 9 Q out W1 10 PRE in +3V@R1 11 CLK in W2 12 D in +3V@R1 13 CLR in !0_TO_W E18 1 I0 in W1 2 I1 in W4 3 I2 in W6 4 I3 in !W7 5 I4 in W8 6 I5 in W5 8 O out !MK_BLK_END 11 I6 in W9 12 I7 in W9 E19 1 I4 in MK_BLK_END 2 I5 in MK_BLK_END 3 I6 in ST_FINAL 4 I1 in MK_BLK_START 5 I2 in ST_REV_CK 8 O out N$3 9 I8 in SHIFT_CK 10 I7 in ST_CK 11 I10 pas N$2 12 I9 pas N$1 13 I3 in DATA E20 1 I0 in !MK_BLK_END 2 I1 in !MK_BLK_END 3 O out MK_BLK_END 4 I0 in !MK_BLK_SYNC 5 I1 in !MK_BLK_SYNC 6 O out MK_BLK_SYNC 8 O out MK_DATA 9 I0 in !MK_DATA 10 I1 in !MK_DATA 11 O out SYNC 12 I0 in !SYNC 13 I1 in !SYNC E21 1 I0 in W1 2 I1 in W4 3 I2 in W2 4 I3 in !W5 5 I4 in W3 6 I5 in AU1 8 O out !MK_BLK_SYNC 11 I6 in !W7 12 I7 in W6 R1 1 1 pas +3V@R1 2 2 pas VCC R2 1 1 pas GND 2 2 pas +3V@R1 R3 1 1 pas +3V@R3 2 2 pas VCC R4 1 1 pas GND 2 2 pas +3V@R3 U$5 AA2 1 io VCC AC2 1 io GND AD2 1 io !MK_BLK_MK AE2 1 io MK_BLK_MK AF1 1 io !MK_BLK_START AF2 1 io MK_END AH1 1 io MK_DATA_SYNC AH2 1 io !MK_END AJ1 1 io !MK_DATA_SYNC AJ2 1 io MK_BLK_START AK1 1 io W1*W5 AK2 1 io W7 AL1 1 io W8 AM1 1 io SH_ST_OUT AM2 1 io W6 AN1 1 io !TP0 AN2 1 io ST_IDLE AP2 1 io SHIFT_I AR2 1 io ST_BLK_MK AS2 1 io AS2 AT1 1 io GND AT2 1 io W4 AU1 1 io AU1 AU2 1 io !MK_DATA AV2 1 io !0_TO_STATE BA2 1 io VCC BC1 1 io SH_ST BC2 1 io GND BD2 1 io ST_IDLE_IN BE2 1 io W3 BF1 1 io TP1 BF2 1 io W9 BH1 1 io BH1 BH2 1 io !0_TO_W BJ2 1 io W1 BK2 1 io DATA BL2 1 io ST_FINAL BM2 1 io !SYNC BN2 1 io SYNC BP2 1 io MK_DATA BR1 1 io ST_CK BR2 1 io SHIFT_CK BS1 1 io ST_REV_CK BS2 1 io MK_BLK_SYNC BT1 1 io GND BT2 1 io !MK_BLK_SYNC BU1 1 io MK_BLK_END BU2 1 io W5 BV1 1 io !MK_BLK_END BV2 1 io W2