// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: cpol_use 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// e1: sn74193 
module m238x (d1, d2, e1, e2, f1, f2, h1, h2, j1, j2, k1, k2, l1, l2, m1, m2, n1, n2, p1, p2, r1, r2, s1, s2, u1, u2, v1, v2);
input d1;
input d2;
output e1;
input e2;
output f1;
inout reg f2;
input h1;
inout reg h2;
input j1;
input j2;
input k1;
input k2;
inout reg l1;
inout reg l2;
input m1;
input m2;
output n1;
input n2;
output p1;
inout reg p2;
input r1;
inout reg r2;
input s1;
input s2;
input u1;
input u2;
inout reg v1;
inout reg v2;

reg f2_m;
reg h2_m;
reg l1_m;
reg l2_m;
reg p2_m;
reg r2_m;
reg v1_m;
reg v2_m;

always @(k2, j2, h1, d1, j1, d1, j1, l2)
  if (h1
                | ~d1 & ~j1) begin
    l2_m <= 1'b0;
  end else
  if (~d1 & j1) begin
    l2_m <= 1'b1;
  end else
  if (~(~(~k2
                  | ~j2))) begin
    l2_m <= ~l2;
  end
always @(k2, j2, h1, d1, j1, d1, j1, l2_m)
  if (h1
                | ~d1 & ~j1) begin
    l2 <= 1'b0;
  end else
  if (~d1 & j1) begin
    l2 <= 1'b1;
  end else
  if (~(~k2
                  | ~j2)) begin
    l2 <= l2_m;
  end
always @(k2, l2, j2, l2, h1, d1, k1, d1, k1, l1)
  if (h1
                | ~d1 & ~k1) begin
    l1_m <= 1'b0;
  end else
  if (~d1 & k1) begin
    l1_m <= 1'b1;
  end else
  if (~(~(~k2 & ~l2
                  | ~j2 & l2))) begin
    l1_m <= ~l1;
  end
always @(k2, l2, j2, l2, h1, d1, k1, d1, k1, l1_m)
  if (h1
                | ~d1 & ~k1) begin
    l1 <= 1'b0;
  end else
  if (~d1 & k1) begin
    l1 <= 1'b1;
  end else
  if (~(~k2 & ~l2
                  | ~j2 & l2)) begin
    l1 <= l1_m;
  end
always @(k2, l2, l1, j2, l2, l1, h1, d1, e2, d1, e2, h2)
  if (h1
                | ~d1 & ~e2) begin
    h2_m <= 1'b0;
  end else
  if (~d1 & e2) begin
    h2_m <= 1'b1;
  end else
  if (~(~(~k2 & ~l2 & ~l1
                  | ~j2 & l2 & l1))) begin
    h2_m <= ~h2;
  end
always @(k2, l2, l1, j2, l2, l1, h1, d1, e2, d1, e2, h2_m)
  if (h1
                | ~d1 & ~e2) begin
    h2 <= 1'b0;
  end else
  if (~d1 & e2) begin
    h2 <= 1'b1;
  end else
  if (~(~k2 & ~l2 & ~l1
                  | ~j2 & l2 & l1)) begin
    h2 <= h2_m;
  end
always @(k2, h2, l2, l1, j2, h2, l2, l1, h1, d1, d2, d1, d2, f2)
  if (h1
                | ~d1 & ~d2) begin
    f2_m <= 1'b0;
  end else
  if (~d1 & d2) begin
    f2_m <= 1'b1;
  end else
  if (~(~(~k2 & ~h2 & ~l2 & ~l1
                  | ~j2 & h2 & l2 & l1))) begin
    f2_m <= ~f2;
  end
always @(k2, h2, l2, l1, j2, h2, l2, l1, h1, d1, d2, d1, d2, f2_m)
  if (h1
                | ~d1 & ~d2) begin
    f2 <= 1'b0;
  end else
  if (~d1 & d2) begin
    f2 <= 1'b1;
  end else
  if (~(~k2 & ~h2 & ~l2 & ~l1
                  | ~j2 & h2 & l2 & l1)) begin
    f2 <= f2_m;
  end
assign e1 = l2 & l1 & h2 & f2;
assign f1 = ~l2 & ~l1 & ~h2 & ~f2;
// e2: sn74193 
always @(u2, s2, r1, m1, s1, m1, s1, v2)
  if (r1
                | ~m1 & ~s1) begin
    v2_m <= 1'b0;
  end else
  if (~m1 & s1) begin
    v2_m <= 1'b1;
  end else
  if (~(~(~u2
                  | ~s2))) begin
    v2_m <= ~v2;
  end
always @(u2, s2, r1, m1, s1, m1, s1, v2_m)
  if (r1
                | ~m1 & ~s1) begin
    v2 <= 1'b0;
  end else
  if (~m1 & s1) begin
    v2 <= 1'b1;
  end else
  if (~(~u2
                  | ~s2)) begin
    v2 <= v2_m;
  end
always @(u2, v2, s2, v2, r1, m1, u1, m1, u1, v1)
  if (r1
                | ~m1 & ~u1) begin
    v1_m <= 1'b0;
  end else
  if (~m1 & u1) begin
    v1_m <= 1'b1;
  end else
  if (~(~(~u2 & ~v2
                  | ~s2 & v2))) begin
    v1_m <= ~v1;
  end
always @(u2, v2, s2, v2, r1, m1, u1, m1, u1, v1_m)
  if (r1
                | ~m1 & ~u1) begin
    v1 <= 1'b0;
  end else
  if (~m1 & u1) begin
    v1 <= 1'b1;
  end else
  if (~(~u2 & ~v2
                  | ~s2 & v2)) begin
    v1 <= v1_m;
  end
always @(u2, v2, v1, s2, v2, v1, r1, m1, n2, m1, n2, r2)
  if (r1
                | ~m1 & ~n2) begin
    r2_m <= 1'b0;
  end else
  if (~m1 & n2) begin
    r2_m <= 1'b1;
  end else
  if (~(~(~u2 & ~v2 & ~v1
                  | ~s2 & v2 & v1))) begin
    r2_m <= ~r2;
  end
always @(u2, v2, v1, s2, v2, v1, r1, m1, n2, m1, n2, r2_m)
  if (r1
                | ~m1 & ~n2) begin
    r2 <= 1'b0;
  end else
  if (~m1 & n2) begin
    r2 <= 1'b1;
  end else
  if (~(~u2 & ~v2 & ~v1
                  | ~s2 & v2 & v1)) begin
    r2 <= r2_m;
  end
always @(u2, r2, v2, v1, s2, r2, v2, v1, r1, m1, m2, m1, m2, p2)
  if (r1
                | ~m1 & ~m2) begin
    p2_m <= 1'b0;
  end else
  if (~m1 & m2) begin
    p2_m <= 1'b1;
  end else
  if (~(~(~u2 & ~r2 & ~v2 & ~v1
                  | ~s2 & r2 & v2 & v1))) begin
    p2_m <= ~p2;
  end
always @(u2, r2, v2, v1, s2, r2, v2, v1, r1, m1, m2, m1, m2, p2_m)
  if (r1
                | ~m1 & ~m2) begin
    p2 <= 1'b0;
  end else
  if (~m1 & m2) begin
    p2 <= 1'b1;
  end else
  if (~(~u2 & ~r2 & ~v2 & ~v1
                  | ~s2 & r2 & v2 & v1)) begin
    p2 <= p2_m;
  end
assign n1 = v2 & v1 & r2 & p2;
assign p1 = ~v2 & ~v1 & ~r2 & ~p2;
// open collector 'wire-or's 
endmodule