// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// c5: c_us 
// c6: c_us 
// e1: sn74h40 
module m240b (n3v3, n_t_14x, n_t_41x, n_t_43x, n_t_44x, n_t_45x, n_t_46x, n_t_47x, n_t_48x, n_t_49x, n_t_50x, n_t_51x, n_t_52x, n_t_53x, n_t_54x, n_t_55x, n_t_56x, n_t_57x, n_t_58x, n_t_59x, n_t_60x, n_t_61x, n_t_62x, n_t_63x, n_t_64x, n_t_65x, n_t_66x, n_t_67x, n_t_68x, n_t_69x, n_t_70x);
input n3v3;
inout n_t_14x;
inout n_t_41x;
input n_t_43x;
input n_t_44x;
input n_t_45x;
inout n_t_46x;
inout n_t_47x;
input n_t_48x;
input n_t_49x;
input n_t_50x;
inout n_t_51x;
inout n_t_52x;
input n_t_53x;
input n_t_54x;
input n_t_55x;
inout n_t_56x;
inout n_t_57x;
input n_t_58x;
input n_t_59x;
input n_t_60x;
inout n_t_61x;
inout n_t_62x;
input n_t_63x;
input n_t_64x;
input n_t_65x;
inout n_t_66x;
inout n_t_67x;
input n_t_68x;
input n_t_69x;
input n_t_70x;


assign n_t_14x = ~(n3v3 & n_t_43x & n3v3 & n_t_41x);
assign n_t_41x = ~(n_t_14x & n_t_44x & n_t_45x & n3v3);
// e2: sn74h40 
assign n_t_46x = ~(n3v3 & n_t_48x & n3v3 & n_t_47x);
assign n_t_47x = ~(n_t_46x & n_t_49x & n_t_50x & n3v3);
// e3: sn74h40 
assign n_t_51x = ~(n3v3 & n_t_53x & n3v3 & n_t_52x);
assign n_t_52x = ~(n_t_51x & n_t_54x & n_t_55x & n3v3);
// e4: sn74h40 
assign n_t_56x = ~(n3v3 & n_t_58x & n3v3 & n_t_57x);
assign n_t_57x = ~(n_t_56x & n_t_59x & n_t_60x & n3v3);
// e5: sn74h40 
assign n_t_61x = ~(n3v3 & n_t_63x & n3v3 & n_t_62x);
assign n_t_62x = ~(n_t_61x & n_t_64x & n_t_65x & n3v3);
// e6: sn74h40 
assign n_t_66x = ~(n3v3 & n_t_68x & n3v3 & n_t_67x);
assign n_t_67x = ~(n_t_66x & n_t_69x & n_t_70x & n3v3);
// open collector 'wire-or's 
endmodule