// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: cpol_use 
// c5: c_us 
// c6: c_us 
// e1: sn74h72 
module m242a (n_t_26x, a1, b1, c1, d1, d2, e1, e2, f1, f2, h1, h2, j1, j2, k1, k2, l1, l2, m1, m2, n1, n2, p1, p2, r1, r2, s1, s2, t2, u1, u2, v1, v2);
input n_t_26x;
inout reg a1;
input b1;
input c1;
input d1;
input d2;
input e1;
input e2;
input f1;
input f2;
inout reg h1;
input h2;
input j1;
output j2;
input k1;
input k2;
input l1;
input l2;
input m1;
input m2;
input n1;
input n2;
inout reg p1;
output p2;
input r1;
input r2;
input s1;
input s2;
input t2;
input u1;
output u2;
input v1;
input v2;

reg a1_m;
reg h1_m;
reg p1_m;

always @(e1, d2, f1, b1, c1, d1, e2, f2, h2, a1)
  if (~d2) begin
    a1_m <= 1'b0;
  end else
  if (~f1) begin
    a1_m <= 1'b1;
  end else
  if (~(e1)) begin
    a1_m <= b1 & c1 & d1? (e2 & f2 & h2? ~a1: 1'b1) : (e2 & f2 & h2? 1'b0: a1);
  end
always @(e1, d2, f1, a1_m)
  if (~d2) begin
    a1 <= 1'b0;
  end else
  if (~f1) begin
    a1 <= 1'b1;
  end else
  if (e1) begin
    a1 <= a1_m;
  end
assign j2 = ~a1;
// e2: sn74h72 
always @(m1, k2, n1, j1, k1, l1, l2, m2, n2, h1)
  if (~k2) begin
    h1_m <= 1'b0;
  end else
  if (~n1) begin
    h1_m <= 1'b1;
  end else
  if (~(m1)) begin
    h1_m <= j1 & k1 & l1? (l2 & m2 & n2? ~h1: 1'b1) : (l2 & m2 & n2? 1'b0: h1);
  end
always @(m1, k2, n1, h1_m)
  if (~k2) begin
    h1 <= 1'b0;
  end else
  if (~n1) begin
    h1 <= 1'b1;
  end else
  if (m1) begin
    h1 <= h1_m;
  end
assign p2 = ~h1;
// e3: sn74h72 
always @(v1, r2, v2, r1, s1, u1, s2, t2, n_t_26x, p1)
  if (~r2) begin
    p1_m <= 1'b0;
  end else
  if (~v2) begin
    p1_m <= 1'b1;
  end else
  if (~(v1)) begin
    p1_m <= r1 & s1 & u1? (s2 & t2 & n_t_26x? ~p1: 1'b1) : (s2 & t2 & n_t_26x? 1'b0: p1);
  end
always @(v1, r2, v2, p1_m)
  if (~r2) begin
    p1 <= 1'b0;
  end else
  if (~v2) begin
    p1 <= 1'b1;
  end else
  if (v1) begin
    p1 <= p1_m;
  end
assign u2 = ~p1;
// open collector 'wire-or's 
endmodule