~/Verilog/bin/topld.pl M246X
info: cpol_use ne cpol_use20_8axial
info: 74h74n ne 7474n
info: 74h74n ne 7474n
info: 74h74n ne 7474n
info: edge_2connector ne edge_con2
warning: making u$2/edge_2connector/ a connector
warning: non-bypass capacitor deleted: c5
~/Verilog/bin/smaller.pl M246X.PLD >vv || (rm vv; exit 1)
0 signals were removed:
~/Verilog/bin/smaller.pl vv >M246XX.PLD || (rm M246XX.PLD; exit 1)
0 signals were removed:
~/Verilog/bin/cupl2v.pl M246XX.PLD >vv || (rm vv; exit 1)
mv vv M246X.v
rm M246XX.PLD