// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: cpol_use 
// e1: sn7495 
module m248b (n_t_10x, n_t_11x, n_t_12x, n_t_13x, n_t_14x, n_t_15x, n_t_16x, n_t_17x, n_t_18x, n_t_19x, n_t_1x, n_t_20x, n_t_21x, n_t_22x, n_t_23x, n_t_24x, n_t_2x, n_t_3x, n_t_4x, n_t_5x, n_t_6x, n_t_7x, n_t_8x, n_t_9x);
inout reg n_t_10x;
inout reg n_t_11x;
inout reg n_t_12x;
input n_t_13x;
input n_t_14x;
input n_t_15x;
input n_t_16x;
input n_t_17x;
input n_t_18x;
input n_t_19x;
input n_t_1x;
input n_t_20x;
output reg n_t_21x;
inout reg n_t_22x;
inout reg n_t_23x;
inout reg n_t_24x;
input n_t_2x;
input n_t_3x;
input n_t_4x;
input n_t_5x;
input n_t_6x;
input n_t_7x;
input n_t_8x;
output reg n_t_9x;


always @(negedge (n_t_8x & ~n_t_6x
                       | n_t_7x & n_t_6x))
  if (~(n_t_8x & ~n_t_6x
                       | n_t_7x & n_t_6x)) begin
    n_t_12x <= n_t_2x & n_t_6x
                    | n_t_1x & ~n_t_6x;
  end
always @(negedge (n_t_8x & ~n_t_6x
                       | n_t_7x & n_t_6x))
  if (~(n_t_8x & ~n_t_6x
                       | n_t_7x & n_t_6x)) begin
    n_t_11x <= n_t_3x & n_t_6x
                    | n_t_12x & ~n_t_6x;
  end
always @(negedge (n_t_8x & ~n_t_6x
                       | n_t_7x & n_t_6x))
  if (~(n_t_8x & ~n_t_6x
                       | n_t_7x & n_t_6x)) begin
    n_t_10x <= n_t_4x & n_t_6x
                    | n_t_11x & ~n_t_6x;
  end
always @(negedge (n_t_8x & ~n_t_6x
                      | n_t_7x & n_t_6x))
  if (~(n_t_8x & ~n_t_6x
                      | n_t_7x & n_t_6x)) begin
    n_t_9x <= n_t_5x & n_t_6x
                   | n_t_10x & ~n_t_6x;
  end
// e2: sn7495 
always @(negedge (n_t_20x & ~n_t_18x
                       | n_t_19x & n_t_18x))
  if (~(n_t_20x & ~n_t_18x
                       | n_t_19x & n_t_18x)) begin
    n_t_24x <= n_t_14x & n_t_18x
                    | n_t_13x & ~n_t_18x;
  end
always @(negedge (n_t_20x & ~n_t_18x
                       | n_t_19x & n_t_18x))
  if (~(n_t_20x & ~n_t_18x
                       | n_t_19x & n_t_18x)) begin
    n_t_23x <= n_t_15x & n_t_18x
                    | n_t_24x & ~n_t_18x;
  end
always @(negedge (n_t_20x & ~n_t_18x
                       | n_t_19x & n_t_18x))
  if (~(n_t_20x & ~n_t_18x
                       | n_t_19x & n_t_18x)) begin
    n_t_22x <= n_t_16x & n_t_18x
                    | n_t_23x & ~n_t_18x;
  end
always @(negedge (n_t_20x & ~n_t_18x
                       | n_t_19x & n_t_18x))
  if (~(n_t_20x & ~n_t_18x
                       | n_t_19x & n_t_18x)) begin
    n_t_21x <= n_t_17x & n_t_18x
                    | n_t_22x & ~n_t_18x;
  end
// open collector 'wire-or's 
endmodule