// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// e1: sn74h10 
module m306x (n_t_33x, n_t_8x, d2, e2, h2, j2, l2, n3v3, n_t_2x, s2, t2);
input n_t_33x;
input n_t_8x;
output d2;
output e2;
input h2;
input j2;
output l2;
input n3v3;
output n_t_2x;
output s2;
inout t2;


wire n_t_57x;
wire n_t_59x;
wire n_t_70x;
wire n_t_71x;
assign n_t_59x = ~(n3v3 & n_t_33x);
assign s2 = ~(n3v3 & t2);
assign n_t_57x = ~(n3v3 & j2 & h2);
// e2: sn74h00 
assign n_t_71x = ~(n_t_57x & n_t_70x);
assign n_t_70x = ~(n_t_71x & n_t_8x);
assign t2 = ~(n_t_59x & n_t_70x);
assign n_t_2x = ~(n_t_70x & n_t_57x);
// open collector 'wire-or's 
endmodule