// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// c5: c_us 
// c6: c_us 
// c7: c_us 
// c8: c_us 
// c9: c_us 
// c10: c_us 
// c11: c_us 
// c12: c_us 
// c13: c_us 
// c14: c_us 
// c15: c_us 
// c16: c_us 
// c17: c_us 
// e1: sn7400 
module m307a (a1, c1, e2, e2q, e2q_l, e4q, e4q_l, f2, h2, j1, j2, k1, k2, l1, l2, m1, n1, n3v3, n_t_10x, n_t_11x, n_t_12x, n_t_13x, n_t_17x, n_t_18x, n_t_19x, n_t_1x, n_t_20x, n_t_22x, n_t_25x, n_t_2x, n_t_4x, n_t_5x, n_t_6x, n_t_7x, n_t_9x, p1, s1, u1, v1);
output a1;
output c1;
output e2;
input e2q;
input e2q_l;
input e4q;
input e4q_l;
output f2;
output h2;
inout j1;
output j2;
output k1;
output k2;
input l1;
output l2;
input m1;
output n1;
input n3v3;
output n_t_10x;
output n_t_11x;
output n_t_12x;
output n_t_13x;
output n_t_17x;
output n_t_18x;
output n_t_19x;
output n_t_1x;
output n_t_20x;
output n_t_22x;
output n_t_25x;
inout n_t_2x;
output n_t_4x;
output n_t_5x;
output n_t_6x;
output n_t_7x;
output n_t_9x;
output p1;
output s1;
output u1;
output v1;


assign k1 = ~e2q_l;
assign h2 = ~e4q_l;
assign f2 = ~e4q;
assign e2 = ~e2q;
// e3a: sn7401 
// j1 = !(n3v3 & m1); 
// n_t_2x = !(n3v3 & l1); 
// n_t_6x = !n_t_2x; 
// n_t_7x = !j1; 
// open collector 'wire-or's 
assign j1 = (n3v3 & m1)? 1'b0: 1'bz;
assign n_t_2x = (n3v3 & l1)? 1'b0: 1'bz;
assign n_t_6x = n_t_2x? ~n_t_2x: 1'bz;
assign n_t_7x = j1? ~j1: 1'bz;
endmodule