// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// c5: c_us 
// c6: c_us 
// c7: c_us 
// c8: c_us 
// c9: c_us 
// c10: c_us 
// c11: cpol_use 
// c12: c_us 
// e1: sn7400 
module m401x (n_t_11x, n_t_15x, n_t_21x, n_t_24x, d2, e2, j2, k2, m2, n2, n_t_12x, n_t_16x, n_t_17x, n_t_30x, p2, r2, s2, t2, v2);
input n_t_11x;
input n_t_15x;
input n_t_21x;
input n_t_24x;
output d2;
inout e2;
input j2;
input k2;
output m2;
output n2;
inout n_t_12x;
output n_t_16x;
output n_t_17x;
output n_t_30x;
output p2;
output r2;
output s2;
output t2;
output v2;


wire n_t_14x;
wire n_t_9x;
assign n_t_12x = ~(k2 & j2);
assign d2 = ~e2;
assign e2 = ~n_t_11x;
assign n_t_30x = ~(n_t_21x & n_t_12x);
// e2: sn74h00 
assign n_t_16x = ~n_t_9x;
assign n_t_17x = ~n_t_9x;
assign n_t_9x = ~(n_t_15x & n_t_14x);
assign n_t_14x = ~(n_t_9x & n_t_24x);
// open collector 'wire-or's 
endmodule