// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// c5: cpol_use 
// c6: c_us 
// c7: c_us 
// c8: c_us 
// c9: c_us 
// c10: c_us 
// c11: c_us 
// c12: c_us 
// c13: c_us 
// c14: c_us 
// c15: c_us 
// c16: c_us 
// c17: c_us 
// c18: c_us 
// c19: c_us 
// c20: c_us 
// c21: c_us 
// c22: c_us 
// c23: c_us 
// c24: c_us 
// c25: c_us 
// c26: c_us 
// c27: c_us 
// e1: sn74h00 
module m420c (n3v3, n_t_15x, n_t_18x, n_t_24x, n_t_32x, n_t_33x, n_t_6x, n10v, n15v, n21v, n_t_10x, n_t_17x, n_t_20x, n_t_27x, n_t_28x, n_t_29x, n_t_31x, n_t_35x, n_t_3x, n_t_4x, n_t_5x, n_t_8x, n_t_9x);
input n3v3;
output n_t_15x;
output n_t_18x;
output n_t_24x;
input n_t_32x;
input n_t_33x;
output n_t_6x;
output n10v;
output n15v;
output n21v;
input n_t_10x;
output n_t_17x;
output n_t_20x;
output n_t_27x;
output n_t_28x;
output n_t_29x;
inout n_t_31x;
output n_t_35x;
inout n_t_3x;
inout n_t_4x;
input n_t_5x;
inout reg n_t_8x;
inout reg n_t_9x;

reg n_t_8x_m;
reg n_t_9x_m;

wire n_t_1x;
wire n_t_2x;
wire n_t_30x;
wire n_t_34x;
assign n_t_34x = ~(n_t_33x & n_t_32x);
assign n_t_29x = ~n_t_30x;
assign n_t_30x = ~(n_t_34x & n_t_31x);
assign n_t_31x = ~(n_t_30x & n_t_32x);
// e2: sn74h74 
always @(n_t_5x, n_t_1x, n3v3, n3v3)
  if (~n_t_1x) begin
    n_t_9x_m <= 1'b0;
  end else
  if (~n3v3) begin
    n_t_9x_m <= 1'b1;
  end else
  if (~(n_t_5x)) begin
    n_t_9x_m <= n3v3;
  end
always @(n_t_5x, n_t_1x, n3v3, n_t_9x_m)
  if (~n_t_1x) begin
    n_t_9x <= 1'b0;
  end else
  if (~n3v3) begin
    n_t_9x <= 1'b1;
  end else
  if (n_t_5x) begin
    n_t_9x <= n_t_9x_m;
  end
assign n_t_4x = ~n_t_9x;
always @(n_t_10x, n_t_1x, n3v3, n3v3)
  if (~n_t_1x) begin
    n_t_8x_m <= 1'b0;
  end else
  if (~n3v3) begin
    n_t_8x_m <= 1'b1;
  end else
  if (~(n_t_10x)) begin
    n_t_8x_m <= n3v3;
  end
always @(n_t_10x, n_t_1x, n3v3, n_t_8x_m)
  if (~n_t_1x) begin
    n_t_8x <= 1'b0;
  end else
  if (~n3v3) begin
    n_t_8x <= 1'b1;
  end else
  if (n_t_10x) begin
    n_t_8x <= n_t_8x_m;
  end
assign n_t_3x = ~n_t_8x;
// e3: sn74h50 
assign n_t_1x = ~(n_t_2x & n_t_8x
                   | n_t_9x & n_t_2x);
assign n_t_2x = ~(n_t_3x & n_t_1x
                   | n_t_1x & n_t_4x);
// open collector 'wire-or's 
endmodule