// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// c5: cpol_use 
// c6: c_us 
// e1: sn7440 
module m452a (n_t_14x, n220_baud, n3v, n880_baud, n_t_12x, n_t_13x, n_t_16x, n_t_21x, n_t_22x, n_t_23x, tp_l, tp_m, tp_n);
input n_t_14x;
inout reg n220_baud;
output n3v;
output n880_baud;
input n_t_12x;
input n_t_13x;
output n_t_16x;
output n_t_21x;
output n_t_22x;
output n_t_23x;
inout tp_l;
inout reg tp_m;
inout tp_n;

reg n220_baud_m;

assign n880_baud = ~n_t_13x;
// e2: sn7474 
always @(posedge n_t_13x)
  if (n_t_13x) begin
    tp_m <= tp_n;
  end
assign tp_n = ~tp_m;
always @(tp_m, tp_l)
  if (1'b1) begin
    n220_baud_m <= 1'b0;
  end else
  if (1'b1) begin
    n220_baud_m <= 1'b1;
  end else
  if (~(~tp_m)) begin
    n220_baud_m <= ~tp_l;
  end
always @(tp_m, n220_baud_m)
  if (1'b1) begin
    n220_baud <= 1'b0;
  end else
  if (1'b1) begin
    n220_baud <= 1'b1;
  end else
  if (~tp_m) begin
    n220_baud <= n220_baud_m;
  end
assign tp_l = n220_baud;
// e3: sn7400 
assign n_t_21x = n_t_14x;
assign n_t_16x = ~(~n_t_14x & n_t_12x);
// open collector 'wire-or's 
endmodule