// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: cpol_use 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// c5: c_us 
// c8: c_us 
// c9: c_us 
// c10: c_us 
// c11: c_us 
// c12: c_us 
// c14: c_us 
// e2: sn7440 
module m453a (n_t_18x, n_t_7x, a1, h2, j1, j2, k2, l1, l2, m1, m2, n1, n2, n3v3, n_t_1x, n_t_5x, n_t_61x, n_t_8x, p1, p2, r1, r2, s1, u1, v1);
input n_t_18x;
output n_t_7x;
output a1;
input h2;
output j1;
output j2;
inout reg k2;
output l1;
inout l2;
output m1;
inout reg m2;
output n1;
inout n2;
input n3v3;
output n_t_1x;
output n_t_5x;
output n_t_61x;
output n_t_8x;
output p1;
input p2;
output r1;
inout r2;
output s1;
output u1;
output v1;

reg k2_m;
reg m2_m;

assign j2 = ~h2;
// e3: sn7474 
always @(h2, n3v3, n3v3, n2)
  if (~n3v3) begin
    m2_m <= 1'b0;
  end else
  if (~n3v3) begin
    m2_m <= 1'b1;
  end else
  if (~(h2)) begin
    m2_m <= n2;
  end
always @(h2, n3v3, n3v3, m2_m)
  if (~n3v3) begin
    m2 <= 1'b0;
  end else
  if (~n3v3) begin
    m2 <= 1'b1;
  end else
  if (h2) begin
    m2 <= m2_m;
  end
assign n2 = ~m2;
always @(m2, n3v3, n3v3, l2)
  if (~(~n3v3)) begin
    k2_m <= 1'b0;
  end else
  if (~(~n3v3)) begin
    k2_m <= 1'b1;
  end else
  if (~(~m2)) begin
    k2_m <= ~l2;
  end
always @(m2, n3v3, n3v3, k2_m)
  if (~(~n3v3)) begin
    k2 <= 1'b0;
  end else
  if (~(~n3v3)) begin
    k2 <= 1'b1;
  end else
  if (~m2) begin
    k2 <= k2_m;
  end
assign l2 = k2;
// e4: sn7400 
assign r2 = ~(~n_t_18x);
assign n_t_1x = ~(p2 & ~r2);
assign n_t_61x = ~h2;
// open collector 'wire-or's 
endmodule