// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// c5: c_us 
// c6: c_us 
// c7: c_us 
// c8: c_us 
// c9: c_us 
// c10: c_us 
// c11: c_us 
// c12: c_us 
// c13: c_us 
// c14: c_us 
// c15: c_us 
// c16: c_us 
// c17: c_us 
// c18: c_us 
// c19: c_us 
// c20: cpol_use 
// c21: cpol_use 
// e1: sn7404 
module m594b (n_t_18x, n_t_20x, n_t_21x, n_t_22x, n_t_23x, n_t_24x, n_t_25x, n_t_26x, a1, b1, b2, c1, d1, d2, e1, e2, f1, f2, h1, h2, j1, j2, k1, k2, l1, l2, m1, m2, n1, n2, n3v3, n_t_10x, n_t_11x, n_t_12x, n_t_13x, n_t_14x, n_t_15x, n_t_16x, n_t_17x, n_t_3x, n_t_4x, n_t_5x, n_t_6x, n_t_7x, n_t_8x, n_t_9x, p1, p2, r1, r2, s1, s2, t2, u1, u2, v1, v2);
output n_t_18x;
output n_t_20x;
output n_t_21x;
output n_t_22x;
output n_t_23x;
output n_t_24x;
output n_t_25x;
output n_t_26x;
output a1;
output b1;
output b2;
output c1;
output d1;
output d2;
output e1;
output e2;
output f1;
output f2;
output h1;
output h2;
output j1;
output j2;
output k1;
output k2;
input l1;
output l2;
input m1;
output m2;
output n1;
output n2;
output n3v3;
output n_t_10x;
input n_t_11x;
input n_t_12x;
input n_t_13x;
input n_t_14x;
input n_t_15x;
input n_t_16x;
input n_t_17x;
output n_t_3x;
input n_t_4x;
output n_t_5x;
output n_t_6x;
output n_t_7x;
output n_t_8x;
output n_t_9x;
output p1;
input p2;
input r1;
output r2;
output s1;
input s2;
output t2;
output u1;
input u2;
output v1;
input v2;


assign e1 = ~n_t_14x;
assign d2 = ~n_t_12x;
assign f2 = ~n_t_15x;
assign d1 = ~n_t_13x;
assign c1 = ~n_t_16x;
assign b1 = ~n_t_17x;
// e4: sn7404 
assign n3v3 = 1'b1;
assign n_t_3x = ~l1;
assign k1 = ~n_t_4x;
assign h1 = ~n_t_11x;
// e6: sn7404 
assign n_t_6x = ~r1;
assign n_t_7x = ~v2;
assign n_t_8x = ~u2;
assign n_t_10x = ~p2;
assign n_t_9x = ~s2;
assign n_t_5x = ~m1;
// open collector 'wire-or's 
endmodule