~/Verilog/bin/topld.pl M617B
info: 7440n ne 7420n
info: 7440n ne 7420n
info: 7440n ne 7420n
info: single ne edge_con2
warning: making u$1/single/ a connector
~/Verilog/bin/smaller.pl M617B.PLD >vv || (rm vv; exit 1)
0 signals were removed:
~/Verilog/bin/smaller.pl vv >M617BX.PLD || (rm M617BX.PLD; exit 1)
0 signals were removed:
~/Verilog/bin/cupl2v.pl M617BX.PLD >vv || (rm vv; exit 1)
mv vv M617B.v
rm M617BX.PLD