~/Verilog/bin/topld.pl M617X
info: 7440n ne 7420n
info: 7440n ne 7420n
info: 7440n ne 7420n
info: single ne edge_con2
warning: making u$1/single/ a connector
~/Verilog/bin/smaller.pl M617X.PLD >vv || (rm vv; exit 1)
0 signals were removed:
~/Verilog/bin/smaller.pl vv >M617XX.PLD || (rm M617XX.PLD; exit 1)
0 signals were removed:
~/Verilog/bin/cupl2v.pl M617XX.PLD >vv || (rm vv; exit 1)
mv vv M617X.v
rm M617XX.PLD