// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// c5: c_us 
// c6: cpol_use 
// c7: c_us 
// e1: sn7450 
module m621x (c1, d1, d2, e1, e2, f1, h1, h2, j1, k1, k2, l1, m1, m2, n1, n_t_1x, n_t_2x, n_t_3x, n_t_4x, n_t_5x, n_t_6x, p1, p2, r1, s1, s2);
input c1;
input d1;
input d2;
input e1;
output e2;
input f1;
input h1;
output h2;
input j1;
input k1;
output k2;
input l1;
input m1;
output m2;
input n1;
output n_t_1x;
output n_t_2x;
output n_t_3x;
output n_t_4x;
output n_t_5x;
output n_t_6x;
input p1;
output p2;
input r1;
input s1;
output s2;


wire n_t_13x;
wire n_t_14x;
wire n_t_18x;
wire n_t_20x;
wire n_t_25x;
wire n_t_27x;
assign n_t_14x = ~(c1 & e1
                    | d1 & d2);
assign n_t_13x = ~(d2 & f1
                    | c1 & h1);
// e2: sn74h00 
assign n_t_3x = ~n_t_18x;
assign n_t_1x = ~n_t_14x;
assign n_t_2x = ~n_t_13x;
// e3: sn7450 
assign n_t_18x = ~(c1 & k1
                    | j1 & d2);
assign n_t_20x = ~(c1 & m1
                    | d2 & l1);
// e4: sn74h00 
assign n_t_6x = ~n_t_27x;
assign n_t_5x = ~n_t_25x;
assign n_t_4x = ~n_t_20x;
// e5: sn7450 
assign n_t_25x = ~(d2 & n1
                    | p1 & c1);
assign n_t_27x = ~(d2 & r1
                    | c1 & s1);
// open collector 'wire-or's 
endmodule