// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// e1: sn7402 
module m624x (a1, b1, c1, d1, d2, e1, e2, f1, f2, h1, h2, j1, j2, k1, k2, l1, l2, m1, m2, n1, n2, n_t_12x, n_t_13x, n_t_14x, n_t_15x, n_t_16x, n_t_17x, n_t_18x, n_t_19x, n_t_1x, n_t_20x, n_t_21x, n_t_3x, n_t_5x, n_t_6x, n_t_7x, p1, p2, r1, r2, s1, s2, t2, u1, u2, v1, v2);
input a1;
output b1;
input c1;
input d1;
input d2;
output e1;
input e2;
input f1;
output f2;
output h1;
input h2;
input j1;
output j2;
output k1;
input k2;
input l1;
output l2;
output m1;
input m2;
input n1;
output n2;
output n_t_12x;
output n_t_13x;
output n_t_14x;
output n_t_15x;
output n_t_16x;
output n_t_17x;
output n_t_18x;
output n_t_19x;
output n_t_1x;
output n_t_20x;
output n_t_21x;
output n_t_3x;
output n_t_5x;
output n_t_6x;
output n_t_7x;
output p1;
input p2;
input r1;
output r2;
output s1;
input s2;
output t2;
output u1;
input u2;
input v1;
output v2;


assign n_t_14x = ~(c1
                    | e2);
assign n_t_12x = ~(c1
                    | d1);
assign n_t_1x = ~(c1
                   | a1);
// e2: sn7402 
assign n_t_18x = ~(c1
                    | k2);
assign n_t_17x = ~(c1
                    | j1);
assign n_t_15x = ~(f1
                    | c1);
assign n_t_16x = ~(h2
                    | c1);
// e3: sn7402 
assign n_t_5x = ~(d2
                   | p2);
assign n_t_21x = ~(c1
                    | n1);
assign n_t_19x = ~(l1
                    | c1);
assign n_t_20x = ~(m2
                    | c1);
// e4: sn7402 
assign n_t_13x = ~(v1
                    | c1);
assign n_t_7x = ~u2;
assign n_t_3x = ~(r1
                   | c1);
assign n_t_6x = ~(s2
                   | d2);
// open collector 'wire-or's 
endmodule