// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: cpol_use 
// e1: sn74h50 
module m628x (n3v, n_t_1x, n_t_2x, alt_mdl3_h, alt_mdl3_l, alt_mdl4_h, alt_mdl4_l, data_en, m2, mdl3_h, mdl4_h, n2, n_t_10x, n_t_11x, n_t_4x, n_t_6x, n_t_7x, p1, p2, r1, r2, s1, s2, t2, u1, u2, v2);
input n3v;
input n_t_1x;
input n_t_2x;
inout alt_mdl3_h;
output alt_mdl3_l;
inout alt_mdl4_h;
output alt_mdl4_l;
input data_en;
output m2;
input mdl3_h;
input mdl4_h;
output n2;
output n_t_10x;
output n_t_11x;
input n_t_4x;
output n_t_6x;
output n_t_7x;
output p1;
output p2;
output r1;
output r2;
output s1;
output s2;
output t2;
output u1;
output u2;
output v2;


wire n_t_3x;
wire n_t_5x;
assign n_t_3x = ~(n_t_4x & mdl4_h
                   | data_en & alt_mdl4_h);
assign n_t_5x = ~(data_en & alt_mdl3_h
                   | n_t_4x & mdl3_h);
// e2: sn74h00 
assign alt_mdl3_l = ~(alt_mdl3_h & n3v);
assign alt_mdl4_l = ~(n3v & alt_mdl4_h);
assign n_t_7x = ~(n_t_3x & n3v);
assign n_t_6x = ~(n_t_5x & n3v);
// e3: sn7482 
assign alt_mdl4_h = n_t_1x
                     ^ mdl4_h;
assign gdollar_0 = n_t_1x & mdl4_h;
assign alt_mdl3_h = mdl3_h
                     ^ n_t_2x
                     ^ gdollar_0;
// open collector 'wire-or's 
endmodule