// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// c5: c_us 
// c6: c_us 
// c7: c_us 
// c8: c_us 
// c9: c_us 
// c10: c_us 
// c11: c_us 
// c12: c_us 
// c13: c_us 
// c14: cpol_use 
// c15: cpol_use 
// e1: ds75451n 
// cwrs_l = !wrs_l; 
// crws_l = !erws_l; 
// e2: ds75451n 
// ccrcs_l = !crcs_l; 
// cbot_l = !ebot_l; 
// e3: ds75451n 
// ctur_l = !rtur_l; 
// crd1_l = !xrd1_l; 
// e4: ds75451n 
// csdwn_l = !rsdwn_l; 
// crd0_l = !xrd0_l; 
// e5: ds75451n 
// c7ch_l = !r7ch_l; 
// cvpe_l = !vpe_l; 
// e6: ds75451n 
// cselr_l = !selr_l; 
// cwrl_l = !ewrl_l; 
// e7: ds75451n 
// crd3_l = !xrd3_l; 
// crd2_l = !xrd2_l; 
// e8: ds75451n 
// crd4_l = !xrd4_l; 
// crds_l = !rds_l; 
// e9: ds75451n 
// clrce_l = !lrce_l; 
// ceot_l = !eeot_l; 
// e10: ds75451n 
// clrcs_l = !lrcs_l; 
// ccrce_l = !crce_l; 
// e11: ds75451n 
// crd6_l = !xrd6_l; 
// crd5_l = !xrd5_l; 
// e12: ds75451n 
// crd7_l = !xrd7_l; 
// crdp_l = !xrdp_l; 
// e13: ds75451n 
// cfmk_l = !fmk_l; 
// open collector 'wire-or's 
module m640c (c7ch_l, cbot_l, ccrce_l, ccrcs_l, ceot_l, cfmk_l, clrce_l, clrcs_l, crce_l, crcs_l, crd0_l, crd1_l, crd2_l, crd3_l, crd4_l, crd5_l, crd6_l, crd7_l, crdp_l, crds_l, crws_l, csdwn_l, cselr_l, ctur_l, cvpe_l, cwrl_l, cwrs_l, ebot_l, eeot_l, erws_l, ewrl_l, fmk_l, lrce_l, lrcs_l, n_t_1x, n_t_2x, n_t_3x, r7ch_l, rds_l, rsdwn_l, rtur_l, selr_l, vpe_l, wrs_l, xrd0_l, xrd1_l, xrd2_l, xrd3_l, xrd4_l, xrd5_l, xrd6_l, xrd7_l, xrdp_l);
output c7ch_l;
output cbot_l;
output ccrce_l;
output ccrcs_l;
output ceot_l;
output cfmk_l;
output clrce_l;
output clrcs_l;
input crce_l;
input crcs_l;
output crd0_l;
output crd1_l;
output crd2_l;
output crd3_l;
output crd4_l;
output crd5_l;
output crd6_l;
output crd7_l;
output crdp_l;
output crds_l;
output crws_l;
output csdwn_l;
output cselr_l;
output ctur_l;
output cvpe_l;
output cwrl_l;
output cwrs_l;
input ebot_l;
input eeot_l;
input erws_l;
input ewrl_l;
input fmk_l;
input lrce_l;
input lrcs_l;
output n_t_1x;
output n_t_2x;
output n_t_3x;
input r7ch_l;
input rds_l;
input rsdwn_l;
input rtur_l;
input selr_l;
input vpe_l;
input wrs_l;
input xrd0_l;
input xrd1_l;
input xrd2_l;
input xrd3_l;
input xrd4_l;
input xrd5_l;
input xrd6_l;
input xrd7_l;
input xrdp_l;


assign c7ch_l = r7ch_l? ~r7ch_l: 1'bz;
assign cbot_l = ebot_l? ~ebot_l: 1'bz;
assign ccrce_l = crce_l? ~crce_l: 1'bz;
assign ccrcs_l = crcs_l? ~crcs_l: 1'bz;
assign ceot_l = eeot_l? ~eeot_l: 1'bz;
assign cfmk_l = fmk_l? ~fmk_l: 1'bz;
assign clrce_l = lrce_l? ~lrce_l: 1'bz;
assign clrcs_l = lrcs_l? ~lrcs_l: 1'bz;
assign crd0_l = xrd0_l? ~xrd0_l: 1'bz;
assign crd1_l = xrd1_l? ~xrd1_l: 1'bz;
assign crd2_l = xrd2_l? ~xrd2_l: 1'bz;
assign crd3_l = xrd3_l? ~xrd3_l: 1'bz;
assign crd4_l = xrd4_l? ~xrd4_l: 1'bz;
assign crd5_l = xrd5_l? ~xrd5_l: 1'bz;
assign crd6_l = xrd6_l? ~xrd6_l: 1'bz;
assign crd7_l = xrd7_l? ~xrd7_l: 1'bz;
assign crdp_l = xrdp_l? ~xrdp_l: 1'bz;
assign crds_l = rds_l? ~rds_l: 1'bz;
assign crws_l = erws_l? ~erws_l: 1'bz;
assign csdwn_l = rsdwn_l? ~rsdwn_l: 1'bz;
assign cselr_l = selr_l? ~selr_l: 1'bz;
assign ctur_l = rtur_l? ~rtur_l: 1'bz;
assign cvpe_l = vpe_l? ~vpe_l: 1'bz;
assign cwrl_l = ewrl_l? ~ewrl_l: 1'bz;
assign cwrs_l = wrs_l? ~wrs_l: 1'bz;
endmodule