~/Verilog/bin/topld.pl M640X
warning: making ak2/1,6/ a connector
warning: making as2/1,6/ a connector
warning: making bh2/1,6/ a connector
info: cpol_use ne cpol_use20_8axial
info: cpol_use ne cpol_use20_8axial
info: ds75451n ne dil08
info: ds75451n ne dil08
info: ds75451n ne dil08
info: ds75451n ne dil08
info: ds75451n ne dil08
info: ds75451n ne dil08
info: ds75451n ne dil08
info: ds75451n ne dil08
info: ds75451n ne dil08
info: ds75451n ne dil08
info: ds75451n ne dil08
info: ds75451n ne dil08
info: ds75451n ne dil08
info: double ne edge_con4
warning: making u$1/double/ a connector
~/Verilog/bin/smaller.pl M640X.PLD >vv || (rm vv; exit 1)
0 signals were removed:
~/Verilog/bin/smaller.pl vv >M640XX.PLD || (rm M640XX.PLD; exit 1)
0 signals were removed:
~/Verilog/bin/cupl2v.pl M640XX.PLD >vv || (rm vv; exit 1)
mv vv M640X.v
rm M640XX.PLD