~/Verilog/bin/topld.pl M650X
info: 1n4154 ne 1n4148do35_10
warning: making d1/1n4154/ a connector
info: 1n914 ne 1n4148do35_10
warning: making d10/1n914/ a connector
info: 1n914 ne 1n4148do35_10
warning: making d11/1n914/ a connector
info: 1n914 ne 1n4148do35_10
warning: making d12/1n914/ a connector
info: 1n914 ne 1n4148do35_10
warning: making d13/1n914/ a connector
info: 1n914 ne 1n4148do35_10
warning: making d14/1n914/ a connector
info: 1n914 ne 1n4148do35_10
warning: making d15/1n914/ a connector
info: 1n914 ne 1n4148do35_10
warning: making d16/1n914/ a connector
info: 1n4154 ne 1n4148do35_10
warning: making d2/1n4154/ a connector
info: 1n4154 ne 1n4148do35_10
warning: making d3/1n4154/ a connector
info: 1n4154 ne 1n4148do35_10
warning: making d4/1n4154/ a connector
info: 1n4154 ne 1n4148do35_10
warning: making d5/1n4154/ a connector
info: 1n4154 ne 1n4148do35_10
warning: making d6/1n4154/ a connector
info: 1n4154 ne 1n4148do35_10
warning: making d7/1n4154/ a connector
info: 1n4154 ne 1n4148do35_10
warning: making d8/1n4154/ a connector
info: 1n4154 ne 1n4148do35_10
warning: making d9/1n4154/ a connector
info: 7410n ne dil14
info: mps6534 ne 2n5415
warning: making q1/mps6534/ a connector
info: mps6534 ne 2n5415
warning: making q2/mps6534/ a connector
info: pn3569 ne 2n2219
warning: making q3/pn3569/ a connector
info: mps6534 ne 2n5415
warning: making q4/mps6534/ a connector
info: mps6534 ne 2n5415
warning: making q5/mps6534/ a connector
info: pn3569 ne 2n2219
warning: making q6/pn3569/ a connector
info: mps6534 ne 2n5415
warning: making q7/mps6534/ a connector
info: mps6534 ne 2n5415
warning: making q8/mps6534/ a connector
info: pn3569 ne 2n2219
warning: making q9/pn3569/ a connector
info: edge_1 ne edge_con1
warning: making u$3/edge_1/ a connector
warning: non-bypass capacitor deleted: c1
warning: non-bypass capacitor deleted: c2
warning: non-bypass capacitor deleted: c3
warning: non-bypass capacitor deleted: c4
~/Verilog/bin/smaller.pl M650X.PLD >vv || (rm vv; exit 1)
0 signals were removed:
~/Verilog/bin/smaller.pl vv >M650XX.PLD || (rm M650XX.PLD; exit 1)
0 signals were removed:
~/Verilog/bin/cupl2v.pl M650XX.PLD >vv || (rm vv; exit 1)
mv vv M650X.v
rm M650XX.PLD