// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: cpol_use 
// c2: cpol_use 
// c3: cpol_use 
// c4: c_us 
// c5: c_us 
// e1: sn7401 
// n_t_9x = !(n_t_7x & n_t_8x); 
// n_t_3x = !(n_t_1x & n_t_2x); 
// n_t_4x = !n_t_3x; 
// n_t_10x = !n_t_9x; 
// e2: sn7401 
// n_t_15x = !(n_t_13x & n_t_14x); 
// n_t_16x = !n_t_15x; 
// open collector 'wire-or's 
module m660a (n_t_10x, n_t_12x, n_t_13x, n_t_14x, n_t_15x, n_t_16x, n_t_18x, n_t_1x, n_t_2x, n_t_3x, n_t_4x, n_t_6x, n_t_7x, n_t_8x, n_t_9x);
output n_t_10x;
output n_t_12x;
input n_t_13x;
input n_t_14x;
inout n_t_15x;
output n_t_16x;
output n_t_18x;
input n_t_1x;
input n_t_2x;
inout n_t_3x;
output n_t_4x;
output n_t_6x;
input n_t_7x;
input n_t_8x;
inout n_t_9x;


assign n_t_10x = n_t_9x? ~n_t_9x: 1'bz;
assign n_t_15x = (n_t_13x & n_t_14x)? 1'b0: 1'bz;
assign n_t_16x = n_t_15x? ~n_t_15x: 1'bz;
assign n_t_3x = (n_t_1x & n_t_2x)? 1'b0: 1'bz;
assign n_t_4x = n_t_3x? ~n_t_3x: 1'bz;
assign n_t_9x = (n_t_7x & n_t_8x)? 1'b0: 1'bz;
endmodule