// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// e1: sn7410 
module m661x (n_t_10x, n_t_11x, n_t_15x, n_t_17x, n_t_18x, n_t_1x, n_t_20x, n_t_22x, n_t_2x, n_t_3x, n_t_5x, n_t_6x, n_t_7x, n_t_8x, n_t_9x);
output n_t_10x;
output n_t_11x;
input n_t_15x;
output n_t_17x;
output n_t_18x;
input n_t_1x;
input n_t_20x;
input n_t_22x;
input n_t_2x;
output n_t_3x;
input n_t_5x;
output n_t_6x;
input n_t_7x;
input n_t_8x;
input n_t_9x;


assign n_t_17x = ~(n_t_8x & n_t_7x & n_t_22x);
assign n_t_10x = ~(n_t_9x & n_t_5x & n_t_15x);
assign n_t_3x = ~(n_t_2x & n_t_1x & n_t_20x);
// open collector 'wire-or's 
endmodule