// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// c5: c_us 
// c6: c_us 
// c7: c_us 
// c8: cpol_use 
// c10: cpol_use 
// c11: cpol_use 
// e1: sn7452 
module m688x (n_t_12x, n_t_22x, n_t_3x, b1, c1, d1, d2, e1, e2, f2, h1, h2, j2, k1, k2, l1, l2, m2, n1, n2, n_t_11x, n_t_14x, n_t_1x, n_t_20x, n_t_23x, n_t_2x, n_t_5x, p1, p2, r1, r2, s1, t2, u2, v2);
input n_t_12x;
input n_t_22x;
input n_t_3x;
input b1;
input c1;
input d1;
output d2;
inout e1;
input e2;
input f2;
input h1;
input h2;
input j2;
output k1;
input k2;
output l1;
input l2;
input m2;
input n1;
input n2;
output n_t_11x;
output n_t_14x;
input n_t_1x;
inout n_t_20x;
output n_t_23x;
output n_t_2x;
output n_t_5x;
output p1;
input p2;
input r1;
inout r2;
input s1;
input t2;
input u2;
input v2;


assign e1 = k2 & j2
             | h2 & f2 & e2
             | d1 & c1
             | b1 & n_t_1x;
// e2: sn7404 
assign n_t_20x = ~n_t_22x;
assign n_t_23x = n_t_20x;
// e3: sn7405 
// n_t_14x = !n_t_12x; 
// n_t_11x = !n1; 
// l1 = !r2; 
// k1 = !e1; 
// n_t_2x = !h1; 
// n_t_5x = !n_t_3x; 
// e4: sn7452 
assign r2 = v2 & u2
             | t2 & r1 & s1
             | p2 & n2
             | l2 & m2;
// open collector 'wire-or's 
assign k1 = e1? ~e1: 1'bz;
assign l1 = r2? ~r2: 1'bz;
assign n_t_11x = n1? ~n1: 1'bz;
assign n_t_14x = n_t_12x? ~n_t_12x: 1'bz;
assign n_t_2x = h1? ~h1: 1'bz;
assign n_t_5x = n_t_3x? ~n_t_3x: 1'bz;
endmodule