// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: cpol_use 
// c2: cpol_use 
// c3: c_us 
// c4: c_us 
// c5: c_us 
// c6: c_us 
// c7: c_us 
// c8: cpol_use 
// c9: c_us 
// c10: c_us 
// c11: c_us 
// c12: c_us 
// c13: c_us 
// c14: c_us 
// e1: sn7474 
module m700e (n_t_17x, n_t_20x, n_t_26x, n_t_30x, n_t_33x, n_t_3x, filter_input, mftp0, mftp1, mftp2, mfts0_h, mfts0_l, mfts1_h, mfts1_l, mfts2_h, mfts2_l, n_t_11x, n_t_12x, n_t_22x, n_t_25x, n_t_28x, n_t_32x, n_t_4x, power_clear_l, restart, run);
input n_t_17x;
input n_t_20x;
input n_t_26x;
input n_t_30x;
input n_t_33x;
input n_t_3x;
output filter_input;
output mftp0;
inout mftp1;
output mftp2;
inout mfts0_h;
inout mfts0_l;
inout reg mfts1_h;
output mfts1_l;
inout reg mfts2_h;
inout mfts2_l;
output n_t_11x;
output n_t_12x;
output n_t_22x;
output n_t_25x;
output n_t_28x;
output n_t_32x;
output n_t_4x;
input power_clear_l;
input restart;
input run;

reg mfts1_h_m;
reg mfts2_h_m;

wire n_t_18x;
wire n_t_19x;
wire n_t_21x;
wire n_t_35x;
wire n_t_5x;
always @(mfts0_h, n_t_35x, 1'b1)
  if (n_t_35x) begin
    mfts1_h_m <= 1'b0;
  end else
  if (~(mfts0_h)) begin
    mfts1_h_m <= 1'b1;
  end
always @(mfts0_h, n_t_35x, mfts1_h_m)
  if (n_t_35x) begin
    mfts1_h <= 1'b0;
  end else
  if (mfts0_h) begin
    mfts1_h <= mfts1_h_m;
  end
assign mfts1_l = ~mfts1_h;
always @(mftp1, n_t_5x, 1'b1)
  if (n_t_5x) begin
    mfts2_h_m <= 1'b0;
  end else
  if (~(mftp1)) begin
    mfts2_h_m <= 1'b1;
  end
always @(mftp1, n_t_5x, mfts2_h_m)
  if (n_t_5x) begin
    mfts2_h <= 1'b0;
  end else
  if (mftp1) begin
    mfts2_h <= mfts2_h_m;
  end
assign mfts2_l = ~mfts2_h;
// e2: sn7400 
assign n_t_5x = ~(~n_t_3x & power_clear_l);
assign n_t_35x = ~(power_clear_l & mfts2_l);
// e3: sn7400 
assign n_t_18x = ~(n_t_17x & restart);
assign n_t_21x = ~(n_t_18x & run);
assign mfts0_h = ~mfts0_l;
// e4: sn7400 
assign n_t_22x = ~(mfts0_l & ~n_t_20x);
assign n_t_25x = ~(~n_t_20x & ~n_t_26x);
assign mftp0 = n_t_20x;
// e5: sn7400 
assign n_t_28x = ~(n_t_26x & ~mftp1);
assign mftp1 = ~(~n_t_30x);
// e6: sn7400 
assign n_t_32x = ~(~mftp1 & ~n_t_33x);
assign n_t_4x = ~(n_t_33x & ~n_t_3x);
// e7: sn7400 
assign mftp2 = n_t_3x;
// e8: sn7400 
assign mfts0_l = ~(n_t_18x & n_t_19x);
assign n_t_19x = ~(mfts0_l & n_t_21x);
// open collector 'wire-or's 
endmodule