~/Verilog/bin/topld.pl M7010B
info: cpol_use ne cpol_use20_8axial
info: cpol_use ne cpol_use20_8axial
warning: making dl1/16_05529/ a connector
info: 7402n ne dil14
info: 7485n ne dil16
info: n8263 ne dil24
info: n8202 ne dil24
info: 7402n ne dil14
info: 7485n ne dil16
info: 7400n ne dil14
info: 7402n ne dil14
info: 7440n ne 7420n
info: n8263 ne dil24
info: n8263 ne dil24
info: 7400n ne dil14
info: 9601 ne dil14
warning: making e23/9601/ a connector
info: n8263 ne dil24
info: 7400n ne dil14
info: 7485n ne dil16
info: n8263 ne dil24
info: n8202 ne dil24
info: double ne edge_con4
warning: making u$3/double/ a connector
warning: non-bypass capacitor deleted: c26
warning: non-bypass capacitor deleted: c27
~/Verilog/bin/smaller.pl M7010B.PLD >vv || (rm vv; exit 1)
4 signals were removed:
  gdollar_0: 'b'0
  gdollar_1: 'b'0
  n_t_125x: !n_t_51x
  n_t_134x: !n_t_149x
~/Verilog/bin/smaller.pl vv >M7010BX.PLD || (rm M7010BX.PLD; exit 1)
0 signals were removed:
~/Verilog/bin/cupl2v.pl M7010BX.PLD >vv || (rm vv; exit 1)
mv vv M7010B.v
rm M7010BX.PLD