// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c6: cpol_use 
// c7: cpol_use 
// c8: c_us 
// c9: c_us 
// c10: c_us 
// c11: c_us 
// c12: c_us 
// c13: c_us 
// c14: c_us 
// c15: c_us 
// c16: c_us 
// c17: c_us 
// c18: c_us 
// c19: c_us 
// c20: c_us 
// c21: c_us 
// c22: cpol_use 
// e1: sn7400 
module m701d (n_t_14x, n_t_26x, n_t_32x, , clear_x, clear_y, initialize, interrupt_l, iop1, iop2, iop4, light_pen, load_x, load_y, mb10=1, mb11=1, mb3=0, mb4=0, mb5=0, mb6=1, mb7=0, mb7=1, mb8=0, mb8=1, mb9=0, n15v, n_t_18x, n_t_19x, n_t_20x, n_t_24x, n_t_38x, n_t_39x, n_t_40x, n_t_48x, n_t_50x, n_t_8x, skip_l, z_axis);
input n_t_14x;
output n_t_26x;
input n_t_32x;
input ;
output clear_x;
output clear_y;
input initialize;
output interrupt_l;
input iop1;
input iop2;
input iop4;
output light_pen;
output load_x;
output load_y;
output mb10=1;
output mb11=1;
output mb3=0;
input mb4=0;
input mb5=0;
input mb6=1;
output mb7=0;
output mb7=1;
input mb8=0;
input mb8=1;
output mb9=0;
output n15v;
output n_t_18x;
inout n_t_19x;
inout n_t_20x;
input n_t_24x;
output n_t_38x;
output n_t_39x;
output n_t_40x;
output n_t_48x;
output n_t_50x;
output n_t_8x;
output skip_l;
output z_axis;

reg br0=1_m;
reg br1=1_m;
reg light_pen_flag_m;

reg light_pen_flag;
reg br0=1;
reg br1=1;
wire br0=0;
wire br1=0;
wire n_t_11x;
wire n_t_12x;
wire n_t_13x;
wire n_t_16x;
wire n_t_1x;
wire n_t_27x;
wire n_t_33x;
wire n_t_36x;
wire n_t_3x;
wire n_t_47x;
wire n_t_4x;
wire n_t_5x;
assign n_t_13x = ~( & ~n_t_14x);
// e2: sn7474 
always @(initialize, n_t_16x, n_t_13x, 1'b0)
  if (~n_t_16x) begin
    light_pen_flag_m <= 1'b0;
  end else
  if (~n_t_13x) begin
    light_pen_flag_m <= 1'b1;
  end else
  if (~(initialize)) begin
    light_pen_flag_m <= 1'b0;
  end
always @(initialize, n_t_16x, n_t_13x, light_pen_flag_m)
  if (~n_t_16x) begin
    light_pen_flag <= 1'b0;
  end else
  if (~n_t_13x) begin
    light_pen_flag <= 1'b1;
  end else
  if (initialize) begin
    light_pen_flag <= light_pen_flag_m;
  end
// e3: sn7400 
assign load_y = ~(~(~n_t_4x & iop2));
assign load_x = ~(~(iop2 & ~n_t_5x));
// e4: sn7460 
// n_t_20x = !light_pen_flag; 
// n_t_8x = !n_t_20x; 
// n_t_19x = !(light_pen_flag & !n_t_3x & mb9= 0 & iop1; 
// n_t_18x = !n_t_19x; 
// e5: sn7420 
// e6: sn7410 
assign n_t_16x = ~mb9=;
// e7: sn7420 
assign clear_y = ~(~n_t_4x & iop1 & n_t_47x);
assign clear_x = ~(~n_t_5x & n_t_47x & iop1);
// e8: sn7410 
assign n_t_38x = ~(br1=1 & br0=);
assign n_t_39x = ~(br1=0 & br0=);
assign n_t_40x = ~(br0=0 & n_t_24x & br1=);
// e9: sn7400 
assign n_t_11x = ~(n_t_5x & n_t_4x);
assign n_t_47x = ~mb10=;
// e10: sn7474 
always @(n_t_12x, initialize, mb10=)
  if (initialize) begin
    br0=1_m <= 1'b1;
  end else
  if (~(~n_t_12x)) begin
    br0=1_m <= mb10=;
  end
always @(n_t_12x, initialize, br0=1_m)
  if (initialize) begin
    br0=1 <= 1'b1;
  end else
  if (~n_t_12x) begin
    br0=1 <= br0=1_m;
  end
assign br0=0 = ~br0=;
always @(n_t_12x, initialize, mb11=)
  if (initialize) begin
    br1=1_m <= 1'b1;
  end else
  if (~(~n_t_12x)) begin
    br1=1_m <= mb11=;
  end
always @(n_t_12x, initialize, br1=1_m)
  if (initialize) begin
    br1=1 <= 1'b1;
  end else
  if (~n_t_12x) begin
    br1=1 <= br1=1_m;
  end
assign br1=0 = ~br1=;
// e11: sn7410 
assign n_t_3x = ~(~n_t_1x & mb8=1 & mb7=);
assign n_t_5x = ~(mb8=1 & mb7=);
assign n_t_4x = ~(mb8=0 & ~n_t_1x & mb7=);
// e12: sn7400 
assign n_t_27x = ~( & n_t_32x);
assign n_t_33x = ~(n_t_36x & ~n_t_32x);
// e13: sn7420 
assign n_t_1x = ~(mb4=0 & mb5=0 & mb6=1 & mb3=);
// e14: sn7400 
assign n_t_12x = ~(iop4 & ~n_t_3x);
assign n_t_36x = ~(n_t_11x & iop4);
// open collector 'wire-or's 
assign n_t_18x = n_t_19x? ~n_t_19x: 1'bz;
assign n_t_19x = (light_pen_flag & ~n_t_3x & mb9=)? 1'b0: 1'bz;
assign n_t_20x = light_pen_flag? ~light_pen_flag: 1'bz;
assign n_t_8x = n_t_20x? ~n_t_20x: 1'bz;
endmodule