~/Verilog/bin/topld.pl M701D
info: cpol_use ne cpol_use20_8axial
info: cpol_use ne cpol_use20_8axial
info: cpol_use ne cpol_use20_8axial
info: 1n3606 ne 1n4148do35_10
warning: making d1/1n3606/ a connector
info: 1n3606 ne 1n4148do35_10
warning: making d2/1n3606/ a connector
info: 1n3606 ne 1n4148do35_10
warning: making d3/1n3606/ a connector
info: 1n3606 ne 1n4148do35_10
warning: making d4/1n3606/ a connector
info: 1n3606 ne 1n4148do35_10
warning: making d5/1n3606/ a connector
info: 1n3653 ne 1n4148do35_10
warning: making d6/1n3653/ a connector
info: 1n3606 ne 1n4148do35_10
warning: making d7/1n3606/ a connector
info: 1n3653 ne 1n4148do35_10
warning: making d8/1n3653/ a connector
info: 1n3653 ne 1n4148do35_10
warning: making d9/1n3653/ a connector
info: 7400n ne dil14
info: 7410n ne dil14
info: 7400n ne dil14
info: 7400n ne dil14
info: 7400n ne dil14
info: 7460n ne dil14
info: 7410n ne dil14
info: 7410n ne dil14
info: 7400n ne dil14
info: 2n3009 ne 2n2102
warning: making q1/2n3009/ a connector
info: 2n3009 ne 2n2102
warning: making q2/2n3009/ a connector
info: 2n3009 ne 2n2102
warning: making q3/2n3009/ a connector
info: 2n3009 ne 2n2102
warning: making q4/2n3009/ a connector
info: mps6534 ne 2n2905
warning: making q5/mps6534/ a connector
info: mps6534 ne 2n2905
warning: making q6/mps6534/ a connector
info: mps6534 ne 2n2905
warning: making q7/mps6534/ a connector
info: double ne edge_con4
warning: making u$1/double/ a connector
warning: non-bypass capacitor deleted: c1
warning: non-bypass capacitor deleted: c2
~/Verilog/bin/smaller.pl M701D.PLD >vv || (rm vv; exit 1)
12 signals were removed:
  n_t_10x: !load_y
  n_t_15x: !n_t_3x
  n_t_21x: !n_t_12x
  n_t_22x: !initialize
  n_t_25x: !n_t_14x
  n_t_2x: !n_t_1x
  n_t_30x: !n_t_31x
  n_t_31x: !n_t_32x
  n_t_49x: 'b'1
  n_t_6x: !n_t_5x
  n_t_7x: !n_t_4x
  n_t_9x: !load_x
~/Verilog/bin/smaller.pl vv >M701DX.PLD || (rm M701DX.PLD; exit 1)
0 signals were removed:
~/Verilog/bin/cupl2v.pl M701DX.PLD >vv || (rm vv; exit 1)
mv vv M701D.v
rm M701DX.PLD