// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: cpol_use 
// c2: cpol_use 
// c3: c_us 
// c4: c_us 
// c5: c_us 
// c7: c_us 
// c8: c_us 
// c10: c_us 
// c11: c_us 
// c12: c_us 
// c13: cpol_use 
// c14: cpol_use 
// e1: sn7430 
module m703x (n_t_10x, n_t_30x, n_t_4x, n_t_6x, n_t_7x, n_t_9x, initialize_l, iop2, mb3=0, mb4=0, mb5=1, mb6=0, mb7=0, mb8=0, n_t_15x, n_t_16x, n_t_17x, n_t_23x, n_t_24x, n_t_26x, n_t_28x, n_t_2x, n_t_3x, pwr_low=0, pwr_low=1, pwr_skip, restart, shutdown_l, stop_ok);
input n_t_10x;
input n_t_30x;
input n_t_4x;
input n_t_6x;
input n_t_7x;
input n_t_9x;
output initialize_l;
output iop2;
input mb3=0;
input mb4=0;
input mb5=1;
input mb6=0;
input mb7=0;
input mb8=0;
inout n_t_15x;
output n_t_16x;
input n_t_17x;
output n_t_23x;
inout n_t_24x;
inout n_t_26x;
output n_t_28x;
inout n_t_2x;
output n_t_3x;
output pwr_low=0;
output pwr_low=1;
output pwr_skip;
output restart;
input shutdown_l;
inout stop_ok;


wire n_t_12x;
wire n_t_14x;
wire n_t_19x;
wire n_t_1x;
wire n_t_20x;
wire n_t_29x;
assign pwr_skip = ~(mb8=0 & mb7=0 & mb6=0 & mb5=1 & mb4=0 & mb3=0 & pwr_low=);
// e2: sn7400 
assign n_t_16x = ~(shutdown_l & n_t_14x);
assign n_t_14x = ~(n_t_2x & ~n_t_10x);
assign n_t_12x = ~(~n_t_4x & ~n_t_10x);
// e3: sn7460 
// n_t_26x = !n_t_6x; 
// !n_t_26x = !n_t_26x; 
// n_t_26x = n_t_26x; 
// n_t_28x = !n_t_26x; 
// e4: sn7400 
assign pwr_low=1 = ~(shutdown_l & pwr_low=);
assign pwr_low=0 = ~pwr_low=;
assign n_t_3x = ~n_t_1x;
assign n_t_1x = ~(stop_ok & pwr_low=);
// e5: sn7400 
assign stop_ok = ~n_t_9x;
assign n_t_20x = ~(stop_ok & shutdown_l);
assign n_t_15x = ~(n_t_30x & n_t_29x);
assign n_t_29x = ~(n_t_19x & n_t_15x);
// e6: sn7400 
assign n_t_19x = ~(n_t_1x & n_t_20x);
assign restart = ~n_t_2x;
assign n_t_2x = ~n_t_17x;
// e7: sn7460 
// n_t_24x = !n_t_7x; 
// !n_t_24x = !n_t_24x; 
// n_t_24x = n_t_24x; 
// n_t_23x = !n_t_24x; 
// open collector 'wire-or's 
assign n_t_23x = n_t_24x? ~n_t_24x: 1'bz;
assign n_t_24x = n_t_7x
                  | (~(1'b0))? 1'b0: 1'bz;
assign n_t_26x = n_t_6x
                  | (~(1'b0))? 1'b0: 1'bz;
assign n_t_28x = n_t_26x? ~n_t_26x: 1'bz;
endmodule