~/Verilog/bin/topld.pl M7050D
info: cpol_use ne cpol_use15_5axial
info: cpol_use ne cpol_use20_8axial
info: cpol_use ne cpol_use20_8axial
info: cpol_use ne cpol_use15_5axial
info: 1n3606 ne 1n4148do35_10
warning: making d1/1n3606/ a connector
info: 1n3606 ne 1n4148do35_10
warning: making d2/1n3606/ a connector
info: 7475n ne dil16
info: 7410n ne dil14
info: 7440n ne 7420n
info: 7404n ne dil14
info: 7430n ne dil14
info: 7400n ne dil14
info: 7404n ne dil14
info: 7400n ne dil14
info: 7400n ne dil14
info: 9601 ne dil14
warning: making e3/9601/ a connector
info: 7475n ne dil16
info: 7404n ne dil14
info: 7400n ne dil14
info: mps6531 ne 2n2102
warning: making q1/mps6531/ a connector
info: mps6531 ne 2n2102
warning: making q2/mps6531/ a connector
info: double ne edge_con4
warning: making u$5/double/ a connector
warning: non-bypass capacitor deleted: c1
warning: non-bypass capacitor deleted: c2
warning: non-bypass capacitor deleted: c3
warning: non-bypass capacitor deleted: c4
warning: non-bypass capacitor deleted: c5
warning: non-bypass capacitor deleted: c6
warning: non-bypass capacitor deleted: c7
warning: non-bypass capacitor deleted: c8
warning: non-bypass capacitor deleted: c9
warning: non-bypass capacitor deleted: c10
warning: non-bypass capacitor deleted: c11
warning: non-bypass capacitor deleted: c12
warning: non-bypass capacitor deleted: c13
warning: non-bypass capacitor deleted: c14
warning: non-bypass capacitor deleted: c15
warning: non-bypass capacitor deleted: c16
warning: non-bypass capacitor deleted: c17
warning: non-bypass capacitor deleted: c18
warning: non-bypass capacitor deleted: c19
warning: non-bypass capacitor deleted: c20
warning: non-bypass capacitor deleted: c21
warning: non-bypass capacitor deleted: c22
warning: non-bypass capacitor deleted: c23
warning: non-bypass capacitor deleted: c24
~/Verilog/bin/smaller.pl M7050D.PLD >vv || (rm vv; exit 1)
9 signals were removed:
  ba_l: !ba
  bb_l: !bb
  n_t_32x: !binit_l
  n_t_33x: !clr_flag
  n_t_35x: !out_of_tape_l
  n_t_36x: !rfc_delayed_l
  n_t_38x: !n_t_40x
  n_t_6x: !clr_run_l
  n_t_8x: !n_t_5x
~/Verilog/bin/smaller.pl vv >M7050DX.PLD || (rm M7050DX.PLD; exit 1)
1 signals were removed:
  binit_l: initialize_l
~/Verilog/bin/cupl2v.pl M7050DX.PLD >vv || (rm vv; exit 1)
mv vv M7050D.v
rm M7050DX.PLD