// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// c5: c_us 
// c6: c_us 
// c7: c_us 
// c8: c_us 
// c9: c_us 
// c10: c_us 
// c11: c_us 
// c12: c_us 
// c13: c_us 
// c14: c_us 
// c15: c_us 
// c16: c_us 
// c17: c_us 
// c18: c_us 
// c19: c_us 
// c20: c_us 
// c21: c_us 
// c22: c_us 
// c23: c_us 
// e1: sn7474 
module m705d (n_t_30x, aj2, ba, ba_l, bb, bb_l, binit_l, bn1, bv2, clock1, enable_l, feed_hole, feed_switch, initialize_l, int_request, iob_in_10, iob_in_11, iob_in_4, iob_in_5, iob_in_6, iob_in_7, iob_in_8, iob_in_9, iop1, iop2, iop4, iot_011, iot_012, iot_014_l, mb3_lp_0_rp, mb4_lp_0_rp, mb5_lp_0_rp, mb6_lp_0_rp, mb7_lp_0_rp, mb8_lp_1_rp, n_t_29x, n_t_31x, pwr, rd_hole_1, rd_hole_2, rd_hole_3, rd_hole_4, rd_hole_5, rd_hole_6, rd_hole_7, rd_hole_8, rdr_run_l, shift, shift_l, skip, stop_complete);
input n_t_30x;
inout aj2;
inout ba;
output ba_l;
inout bb;
output bb_l;
inout binit_l;
inout bn1;
inout bv2;
input clock1;
output reg enable_l;
input feed_hole;
input feed_switch;
input initialize_l;
output int_request;
output iob_in_10;
output iob_in_11;
output iob_in_4;
output iob_in_5;
output iob_in_6;
output iob_in_7;
output iob_in_8;
output iob_in_9;
input iop1;
input iop2;
input iop4;
inout iot_011;
inout iot_012;
inout iot_014_l;
input mb3_lp_0_rp;
input mb4_lp_0_rp;
input mb5_lp_0_rp;
input mb6_lp_0_rp;
input mb7_lp_0_rp;
input mb8_lp_1_rp;
output n_t_29x;
inout n_t_31x;
output pwr;
input rd_hole_1;
input rd_hole_2;
input rd_hole_3;
input rd_hole_4;
input rd_hole_5;
input rd_hole_6;
input rd_hole_7;
input rd_hole_8;
inout rdr_run_l;
input shift;
input shift_l;
output skip;
input stop_complete;

reg enable_l_m;
reg n_t_10x_m;
reg n_t_11x_m;
reg n_t_12x_m;
reg n_t_13x_m;
reg n_t_14x_m;
reg n_t_27x_m;
reg n_t_2x_m;
reg n_t_3x_m;
reg n_t_9x_m;
reg rdr_flag_m;
reg rdr_run_m;

reg n_t_2x;
reg n_t_3x;
reg n_t_9x;
reg n_t_10x;
reg n_t_11x;
reg n_t_12x;
reg n_t_13x;
reg n_t_14x;
reg rdr_flag;
reg rdr_run;
reg n_t_23x;
reg n_t_1x;
reg n_t_27x;
wire clr_flag;
wire n_t_24x;
wire n_t_25x;
wire n_t_28x;
wire n_t_5x;
wire rfc_delayed;
always @(aj2, rfc_delayed, rd_hole_8)
  if (~rfc_delayed) begin
    n_t_2x_m <= 1'b0;
  end else
  if (~(aj2)) begin
    n_t_2x_m <= rd_hole_8;
  end
always @(aj2, rfc_delayed, n_t_2x_m)
  if (~rfc_delayed) begin
    n_t_2x <= 1'b0;
  end else
  if (aj2) begin
    n_t_2x <= n_t_2x_m;
  end
always @(aj2, rfc_delayed, rd_hole_7)
  if (~rfc_delayed) begin
    n_t_3x_m <= 1'b0;
  end else
  if (~(aj2)) begin
    n_t_3x_m <= rd_hole_7;
  end
always @(aj2, rfc_delayed, n_t_3x_m)
  if (~rfc_delayed) begin
    n_t_3x <= 1'b0;
  end else
  if (aj2) begin
    n_t_3x <= n_t_3x_m;
  end
// e2: sn7474 
always @(aj2, rfc_delayed, rd_hole_6)
  if (~rfc_delayed) begin
    n_t_9x_m <= 1'b0;
  end else
  if (~(aj2)) begin
    n_t_9x_m <= rd_hole_6;
  end
always @(aj2, rfc_delayed, n_t_9x_m)
  if (~rfc_delayed) begin
    n_t_9x <= 1'b0;
  end else
  if (aj2) begin
    n_t_9x <= n_t_9x_m;
  end
always @(aj2, rfc_delayed, rd_hole_5)
  if (~rfc_delayed) begin
    n_t_10x_m <= 1'b0;
  end else
  if (~(aj2)) begin
    n_t_10x_m <= rd_hole_5;
  end
always @(aj2, rfc_delayed, n_t_10x_m)
  if (~rfc_delayed) begin
    n_t_10x <= 1'b0;
  end else
  if (aj2) begin
    n_t_10x <= n_t_10x_m;
  end
// e3: sn7474 
always @(aj2, rfc_delayed, rd_hole_4)
  if (~rfc_delayed) begin
    n_t_11x_m <= 1'b0;
  end else
  if (~(aj2)) begin
    n_t_11x_m <= rd_hole_4;
  end
always @(aj2, rfc_delayed, n_t_11x_m)
  if (~rfc_delayed) begin
    n_t_11x <= 1'b0;
  end else
  if (aj2) begin
    n_t_11x <= n_t_11x_m;
  end
always @(aj2, rfc_delayed, rd_hole_3)
  if (~rfc_delayed) begin
    n_t_12x_m <= 1'b0;
  end else
  if (~(aj2)) begin
    n_t_12x_m <= rd_hole_3;
  end
always @(aj2, rfc_delayed, n_t_12x_m)
  if (~rfc_delayed) begin
    n_t_12x <= 1'b0;
  end else
  if (aj2) begin
    n_t_12x <= n_t_12x_m;
  end
// e4: sn7474 
always @(aj2, rfc_delayed, rd_hole_2)
  if (~rfc_delayed) begin
    n_t_13x_m <= 1'b0;
  end else
  if (~(aj2)) begin
    n_t_13x_m <= rd_hole_2;
  end
always @(aj2, rfc_delayed, n_t_13x_m)
  if (~rfc_delayed) begin
    n_t_13x <= 1'b0;
  end else
  if (aj2) begin
    n_t_13x <= n_t_13x_m;
  end
always @(aj2, rfc_delayed, rd_hole_1)
  if (~rfc_delayed) begin
    n_t_14x_m <= 1'b0;
  end else
  if (~(aj2)) begin
    n_t_14x_m <= rd_hole_1;
  end
always @(aj2, rfc_delayed, n_t_14x_m)
  if (~rfc_delayed) begin
    n_t_14x <= 1'b0;
  end else
  if (aj2) begin
    n_t_14x <= n_t_14x_m;
  end
// e5: sn7474 
always @(aj2, clr_flag, rdr_run)
  if (~clr_flag) begin
    rdr_flag_m <= 1'b0;
  end else
  if (~(aj2)) begin
    rdr_flag_m <= rdr_run;
  end
always @(aj2, clr_flag, rdr_flag_m)
  if (~clr_flag) begin
    rdr_flag <= 1'b0;
  end else
  if (aj2) begin
    rdr_flag <= rdr_flag_m;
  end
always @(aj2, binit_l, rfc_delayed, 1'b0)
  if (~binit_l) begin
    rdr_run_m <= 1'b0;
  end else
  if (~rfc_delayed) begin
    rdr_run_m <= 1'b1;
  end else
  if (~(aj2)) begin
    rdr_run_m <= 1'b0;
  end
always @(aj2, binit_l, rfc_delayed, rdr_run_m)
  if (~binit_l) begin
    rdr_run <= 1'b0;
  end else
  if (~rfc_delayed) begin
    rdr_run <= 1'b1;
  end else
  if (aj2) begin
    rdr_run <= rdr_run_m;
  end
assign rdr_run_l = ~rdr_run;
// e6: sn7401 
// iob_in_7 = !(n_t_10x & iot_012); 
// iob_in_6 = !(n_t_9x & iot_012); 
// iob_in_5 = !(n_t_3x & iot_012); 
// iob_in_4 = !(iot_012 & n_t_2x); 
// e7: sn7401 
// iob_in_11 = !(n_t_14x & iot_012); 
// iob_in_10 = !(iot_012 & n_t_13x); 
// iob_in_8 = !(n_t_11x & iot_012); 
// iob_in_9 = !(iot_012 & n_t_12x); 
// e8: sn7400 
assign iot_012 = ~(~(iop2 & ~n_t_5x));
assign iot_011 = ~(~(iop1 & ~n_t_5x));
// e9: sn7401 
// n_t_31x = !feed_hole; 
// int_request = !rdr_flag; 
// skip = !(rdr_flag & iot_011); 
// e10: sn7430 
assign n_t_5x = ~(mb3_lp_0_rp & mb4_lp_0_rp & mb7_lp_0_rp & mb8_lp_1_rp & mb8_lp_1_rp & mb6_lp_0_rp & mb5_lp_0_rp);
// e11: sn7474 
always @(posedge shift)
  if (shift) begin
    n_t_23x <= ~bb;
  end
assign ba = ~(~n_t_23x);
always @(posedge shift)
  if (shift) begin
    n_t_1x <= n_t_23x;
  end
assign bb = ~(~n_t_1x);
// e12: sn7474 
always @(stop_complete, shift_l, binit_l, bn1)
  if (~shift_l) begin
    n_t_27x_m <= 1'b0;
  end else
  if (~binit_l) begin
    n_t_27x_m <= 1'b1;
  end else
  if (~(stop_complete)) begin
    n_t_27x_m <= ~bn1;
  end
always @(stop_complete, shift_l, binit_l, n_t_27x_m)
  if (~shift_l) begin
    n_t_27x <= 1'b0;
  end else
  if (~binit_l) begin
    n_t_27x <= 1'b1;
  end else
  if (stop_complete) begin
    n_t_27x <= n_t_27x_m;
  end
always @(clock1, n_t_28x, binit_l, bn1)
  if (~n_t_28x) begin
    enable_l_m <= 1'b0;
  end else
  if (~binit_l) begin
    enable_l_m <= 1'b1;
  end else
  if (~(clock1)) begin
    enable_l_m <= ~bn1;
  end
always @(clock1, n_t_28x, binit_l, enable_l_m)
  if (~n_t_28x) begin
    enable_l <= 1'b0;
  end else
  if (~binit_l) begin
    enable_l <= 1'b1;
  end else
  if (clock1) begin
    enable_l <= enable_l_m;
  end
// e13: sn7440 
assign rfc_delayed = ~(n_t_31x & n_t_30x & n_t_30x & n_t_31x);
// e14: sn7410 
assign clr_flag = ~(~(binit_l & rfc_delayed & ~iot_012));
assign bn1 = ~(rdr_run_l & feed_switch & ~bv2);
assign iot_014_l = ~(iop4 & ~n_t_5x & ~n_t_5x);
// e15: sn7400 
assign ba_l = ~n_t_23x;
assign bb_l = ~n_t_1x;
// e16: sn7400 
assign n_t_28x = ~(stop_complete & bn1);
assign n_t_25x = ~(~ba & ~bb);
assign n_t_24x = ~(n_t_23x & n_t_1x);
assign pwr = ~n_t_27x;
// e17: sn7400 
assign binit_l = ~(~initialize_l);
// e18: sn7400 
assign aj2 = ~(~(clock1 & bv2));
assign bv2 = ~(n_t_24x & n_t_25x);
assign n_t_29x = ~(iot_014_l & rfc_delayed);
// open collector 'wire-or's 
assign int_request = rdr_flag? ~rdr_flag: 1'bz;
assign iob_in_10 = (iot_012 & n_t_13x)? 1'b0: 1'bz;
assign iob_in_11 = (n_t_14x & iot_012)? 1'b0: 1'bz;
assign iob_in_4 = (iot_012 & n_t_2x)? 1'b0: 1'bz;
assign iob_in_5 = (n_t_3x & iot_012)? 1'b0: 1'bz;
assign iob_in_6 = (n_t_9x & iot_012)? 1'b0: 1'bz;
assign iob_in_7 = (n_t_10x & iot_012)? 1'b0: 1'bz;
assign iob_in_8 = (n_t_11x & iot_012)? 1'b0: 1'bz;
assign iob_in_9 = (iot_012 & n_t_12x)? 1'b0: 1'bz;
assign n_t_31x = feed_hole? ~feed_hole: 1'bz;
assign skip = (rdr_flag & iot_011)? 1'b0: 1'bz;
endmodule