~/Verilog/bin/topld.pl M705J
info: cpol_use ne cpol_use20_8axial
info: cpol_use ne cpol_use20_8axial
info: cpol_use ne cpol_use20_8axial
info: cpol_use ne cpol_use20_8axial
info: 1n3606 ne 1n4148do35_10
warning: making d1/1n3606/ a connector
info: 7400n ne dil14
info: 7430n ne dil14
info: 7410n ne dil14
info: 7400n ne dil14
info: 7400n ne dil14
info: 7400n ne dil14
info: 7400n ne dil14
info: 7440n ne 7420n
info: double ne edge_con4
warning: making u$5/double/ a connector
warning: non-bypass capacitor deleted: c23
~/Verilog/bin/smaller.pl M705J.PLD >vv || (rm vv; exit 1)
11 signals were removed:
  n_t_15x: !n_t_1x
  n_t_1x: !bb_l
  n_t_23x: !ba_l
  n_t_26x: !aj2
  n_t_32x: !binit_l
  n_t_33x: !clr_flag
  n_t_34x: !bv2
  n_t_4x: !n_t_23x
  n_t_6x: !iot_012
  n_t_7x: !iot_011
  n_t_8x: !n_t_5x
~/Verilog/bin/smaller.pl vv >M705JX.PLD || (rm M705JX.PLD; exit 1)
2 signals were removed:
  n_t_1x: !bb_l
  n_t_23x: !ba_l
~/Verilog/bin/cupl2v.pl M705JX.PLD >vv || (rm vv; exit 1)
mv vv M705J.v
rm M705JX.PLD