~/Verilog/bin/topld.pl M7065X
info: dec8242 ne 74266n
info: 7475n ne dil16
info: dec8271 ne dil16
info: 7416n ne dil14
info: 7400n ne dil14
info: 7475n ne dil16
info: dec8271 ne dil16
info: 7404n ne dil14
info: 7450n ne dil14
info: 7400n ne dil14
info: 7400n ne dil14
info: dec8242 ne 74266n
info: single ne edge_con2
warning: making u$2/single/ a connector
warning: non-bypass capacitor deleted: c17
warning: non-bypass capacitor deleted: c18
warning: non-bypass capacitor deleted: c19
~/Verilog/bin/smaller.pl M7065X.PLD >vv || (rm vv; exit 1)
9 signals were removed:
  n_t_4x: 'b'1
  n_t_52x: !n_t_49x
  n_t_56x: !l2
  n_t_58x: !k2
  n_t_60x: !n_t_21x
  n_t_64x: !n_t_51x
  n_t_71x: !r1
  n_t_72x: !n_t_16x
  n_t_88x: !n_t_27x
~/Verilog/bin/smaller.pl vv >M7065XX.PLD || (rm M7065XX.PLD; exit 1)
0 signals were removed:
~/Verilog/bin/cupl2v.pl M7065XX.PLD >vv || (rm vv; exit 1)
mv vv M7065X.v
rm M7065XX.PLD