~/Verilog/bin/topld.pl M706D
info: 1n3606 ne diode_sod61b
warning: making d1/1n3606/ a connector
info: 1n3606 ne diode_sod61b
warning: making d2/1n3606/ a connector
info: 1n3606 ne 1n4148do35_10
warning: making d3/1n3606/ a connector
info: d668 ne 1n4148do35_10
warning: making d4/d668/ a connector
info: 1n3606 ne 1n4148do35_10
warning: making d5/1n3606/ a connector
info: 1n3606 ne diode_sod61b
warning: making d6/1n3606/ a connector
info: 7430n ne dil14
info: 7460n ne dil14
info: 7400n ne dil14
info: 7410n ne dil14
info: 7410n ne dil14
info: 7400n ne dil14
info: 7400n ne dil14
info: 7400n ne dil14
info: 7400n ne dil14
info: 7400n ne dil14
info: dec6534 ne _pnp_to92_ebc
warning: making q1/dec6534/ a connector
info: double ne edge_con4
warning: making u$2/double/ a connector
warning: non-bypass capacitor deleted: c24
warning: non-bypass capacitor deleted: c25
~/Verilog/bin/smaller.pl M706D.PLD >vv || (rm vv; exit 1)
6 signals were removed:
  in_last_l: !in_last
  n_t_13x: !n_t_42x
  n_t_1x: !n_t_45x
  n_t_22x: !buffer_strobe
  n_t_32x: !n_t_29x
  n_t_38x: !n_t_39x
~/Verilog/bin/smaller.pl vv >M706DX.PLD || (rm M706DX.PLD; exit 1)
0 signals were removed:
~/Verilog/bin/cupl2v.pl M706DX.PLD >vv || (rm vv; exit 1)
mv vv M706D.v
rm M706DX.PLD