// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// c5: c_us 
// c6: c_us 
// c7: c_us 
// c8: c_us 
// c9: c_us 
// c10: c_us 
// c11: c_us 
// c12: c_us 
// c13: c_us 
// c14: c_us 
// c15: c_us 
// c16: c_us 
// c17: c_us 
// c18: c_us 
// c19: c_us 
// c20: c_us 
// c21: cpol_use 
// c23: c_us 
// e1: sn7430 
module m707d (n_t_2x, ac04, ac05, ac06, ac07, ac08, ac09, ac10, ac11, active, ae1, af1, ah1, al1, ar1, bit6, bit9, bn1, bp1, clr_flag1, clr_flag2, echo, enable, enable_ds, ioclr, irq, line, load_buffer, n2xclk, n3v, n_t_12x, n_t_13x, n_t_15x, n_t_17x, n_t_1x, n_t_63x, serial_out, size, skip, skp_strobe, stop, tx, wait_l);
input n_t_2x;
input ac04;
input ac05;
input ac06;
input ac07;
input ac08;
input ac09;
input ac10;
input ac11;
inout reg active;
input ae1;
input af1;
input ah1;
output al1;
inout ar1;
inout reg bit6;
inout reg bit9;
output reg bn1;
output bp1;
input clr_flag1;
input clr_flag2;
input echo;
input enable;
input enable_ds;
input ioclr;
inout reg irq;
inout reg line;
input load_buffer;
input n2xclk;
input n3v;
input n_t_12x;
input n_t_13x;
input n_t_15x;
input n_t_17x;
output n_t_1x;
output n_t_63x;
output serial_out;
input size;
output skip;
input skp_strobe;
input stop;
output tx;
input wait_l;

reg active_m;
reg bit1_m;
reg bit2_m;
reg bit3_m;
reg bit4_m;
reg bit5_m;
reg bit6_m;
reg bit7_m;
reg bit8_m;
reg bit9_m;
reg bn1_m;
reg irq_m;
reg line_m;
reg n_t_138x_m;
reg n_t_166x_m;
reg n_t_16x_m;

reg bit1;
reg bit8;
reg bit7;
reg bit4;
reg bit5;
reg n_t_166x;
reg n_t_16x;
reg bit2;
reg bit3;
reg n_t_138x;
wire ioclr_l;
wire n_t_10x;
wire n_t_11x;
wire n_t_132x;
wire n_t_161x;
wire n_t_20x;
wire n_t_28x;
wire n_t_35x;
wire n_t_378x;
wire n_t_37x;
wire n_t_381x;
wire n_t_39x;
wire n_t_3x;
wire n_t_42x;
wire n_t_52x;
wire n_t_53x;
wire n_t_54x;
wire n_t_62x;
wire n_t_6x;
wire n_t_9x;
wire selected;
assign n_t_9x = ~(n_t_17x & ae1 & n_t_15x & af1 & n_t_13x & n_t_12x & n3v & n3v);
// e2: sn7474 
always @(n_t_16x, n_t_2x, active, bit1)
  if (n_t_2x) begin
    line_m <= 1'b0;
  end else
  if (~active) begin
    line_m <= 1'b1;
  end else
  if (~(n_t_16x)) begin
    line_m <= bit1;
  end
always @(n_t_16x, n_t_2x, active, line_m)
  if (n_t_2x) begin
    line <= 1'b0;
  end else
  if (~active) begin
    line <= 1'b1;
  end else
  if (n_t_16x) begin
    line <= line_m;
  end
always @(n_t_16x, ioclr_l, n_t_54x, bit2)
  if (~ioclr_l) begin
    bit1_m <= 1'b0;
  end else
  if (~n_t_54x) begin
    bit1_m <= 1'b1;
  end else
  if (~(n_t_16x)) begin
    bit1_m <= bit2;
  end
always @(n_t_16x, ioclr_l, n_t_54x, bit1_m)
  if (~ioclr_l) begin
    bit1 <= 1'b0;
  end else
  if (~n_t_54x) begin
    bit1 <= 1'b1;
  end else
  if (n_t_16x) begin
    bit1 <= bit1_m;
  end
// e3: sn7400 
assign tx = ~(echo & line);
assign n_t_39x = ~(~n_t_16x & ~n_t_6x);
// e4: sn7400 
assign n_t_20x = ~(enable & ~ar1);
assign selected = ~(n_t_9x & enable_ds);
assign ar1 = ~(selected & load_buffer);
// e5: sn7400 
assign n_t_53x = ~(ac06 & ~ar1);
assign n_t_381x = ~(~ar1 & ac07);
assign n_t_378x = ~(ac05 & ~ar1);
assign n_t_3x = ~(~ar1 & ac04);
// e6: sn7474 
always @(n_t_16x, ioclr_l, n_t_3x, bit9)
  if (~ioclr_l) begin
    bit8_m <= 1'b0;
  end else
  if (~n_t_3x) begin
    bit8_m <= 1'b1;
  end else
  if (~(n_t_16x)) begin
    bit8_m <= bit9;
  end
always @(n_t_16x, ioclr_l, n_t_3x, bit8_m)
  if (~ioclr_l) begin
    bit8 <= 1'b0;
  end else
  if (~n_t_3x) begin
    bit8 <= 1'b1;
  end else
  if (n_t_16x) begin
    bit8 <= bit8_m;
  end
always @(n_t_16x, ioclr_l, n_t_20x, 1'b0)
  if (~ioclr_l) begin
    bit9_m <= 1'b0;
  end else
  if (~n_t_20x) begin
    bit9_m <= 1'b1;
  end else
  if (~(n_t_16x)) begin
    bit9_m <= 1'b0;
  end
always @(n_t_16x, ioclr_l, n_t_20x, bit9_m)
  if (~ioclr_l) begin
    bit9 <= 1'b0;
  end else
  if (~n_t_20x) begin
    bit9 <= 1'b1;
  end else
  if (n_t_16x) begin
    bit9 <= bit9_m;
  end
assign al1 = ~bit9;
// e7: sn7400 
assign n_t_37x = ~(~ar1 & ac10);
assign n_t_54x = ~(~ar1 & ac11);
assign n_t_42x = ~(ac08 & ~ar1);
assign n_t_52x = ~(~ar1 & ac09);
// e8: sn7474 
always @(n_t_16x, ioclr_l, n_t_53x, bit7)
  if (~ioclr_l) begin
    bit6_m <= 1'b0;
  end else
  if (~n_t_53x) begin
    bit6_m <= 1'b1;
  end else
  if (~(n_t_16x)) begin
    bit6_m <= bit7;
  end
always @(n_t_16x, ioclr_l, n_t_53x, bit6_m)
  if (~ioclr_l) begin
    bit6 <= 1'b0;
  end else
  if (~n_t_53x) begin
    bit6 <= 1'b1;
  end else
  if (n_t_16x) begin
    bit6 <= bit6_m;
  end
always @(n_t_16x, ioclr_l, n_t_378x, bit8)
  if (~ioclr_l) begin
    bit7_m <= 1'b0;
  end else
  if (~n_t_378x) begin
    bit7_m <= 1'b1;
  end else
  if (~(n_t_16x)) begin
    bit7_m <= bit8;
  end
always @(n_t_16x, ioclr_l, n_t_378x, bit7_m)
  if (~ioclr_l) begin
    bit7 <= 1'b0;
  end else
  if (~n_t_378x) begin
    bit7 <= 1'b1;
  end else
  if (n_t_16x) begin
    bit7 <= bit7_m;
  end
// e9: sn7430 
assign n_t_6x = ~(~bit6 & ~bit7 & ~bit5 & ~bit4 & ~bit3 & ~bit2 & ah1 & ~bit8);
// e10: sn7440 
assign ioclr_l = ~(n3v & ioclr);
// e11: sn7474 
always @(n_t_16x, ioclr_l, n_t_42x, bit5)
  if (~ioclr_l) begin
    bit4_m <= 1'b0;
  end else
  if (~n_t_42x) begin
    bit4_m <= 1'b1;
  end else
  if (~(n_t_16x)) begin
    bit4_m <= bit5;
  end
always @(n_t_16x, ioclr_l, n_t_42x, bit4_m)
  if (~ioclr_l) begin
    bit4 <= 1'b0;
  end else
  if (~n_t_42x) begin
    bit4 <= 1'b1;
  end else
  if (n_t_16x) begin
    bit4 <= bit4_m;
  end
always @(n_t_16x, ioclr_l, n_t_381x, bit6)
  if (~ioclr_l) begin
    bit5_m <= 1'b0;
  end else
  if (~n_t_381x) begin
    bit5_m <= 1'b1;
  end else
  if (~(n_t_16x)) begin
    bit5_m <= bit6;
  end
always @(n_t_16x, ioclr_l, n_t_381x, bit5_m)
  if (~ioclr_l) begin
    bit5 <= 1'b0;
  end else
  if (~n_t_381x) begin
    bit5 <= 1'b1;
  end else
  if (n_t_16x) begin
    bit5 <= bit5_m;
  end
// e12: sn7400 
assign n_t_1x = active;
assign n_t_28x = ~(n_t_10x & n_t_62x);
// e13: sn7410 
assign n_t_132x = ~(clr_flag1 & n3v & selected);
assign n_t_35x = ~(n_t_132x & clr_flag2 & ioclr_l);
assign skip = ~(skp_strobe & ~irq & selected);
// e14: sn7474 
always @(n2xclk, n3v, n_t_16x, n_t_161x)
  if (~n3v) begin
    n_t_166x_m <= 1'b0;
  end else
  if (~n_t_16x) begin
    n_t_166x_m <= 1'b1;
  end else
  if (~(n2xclk)) begin
    n_t_166x_m <= n_t_161x;
  end
always @(n2xclk, n3v, n_t_16x, n_t_166x_m)
  if (~n3v) begin
    n_t_166x <= 1'b0;
  end else
  if (~n_t_16x) begin
    n_t_166x <= 1'b1;
  end else
  if (n2xclk) begin
    n_t_166x <= n_t_166x_m;
  end
assign n_t_63x = ~n_t_166x;
always @(n2xclk, n3v, ioclr_l, n_t_11x)
  if (~n3v) begin
    n_t_16x_m <= 1'b0;
  end else
  if (~ioclr_l) begin
    n_t_16x_m <= 1'b1;
  end else
  if (~(n2xclk)) begin
    n_t_16x_m <= n_t_11x;
  end
always @(n2xclk, n3v, ioclr_l, n_t_16x_m)
  if (~n3v) begin
    n_t_16x <= 1'b0;
  end else
  if (~ioclr_l) begin
    n_t_16x <= 1'b1;
  end else
  if (n2xclk) begin
    n_t_16x <= n_t_16x_m;
  end
// e15: sn7474 
always @(n_t_16x, ioclr_l, n_t_37x, bit3)
  if (~ioclr_l) begin
    bit2_m <= 1'b0;
  end else
  if (~n_t_37x) begin
    bit2_m <= 1'b1;
  end else
  if (~(n_t_16x)) begin
    bit2_m <= bit3;
  end
always @(n_t_16x, ioclr_l, n_t_37x, bit2_m)
  if (~ioclr_l) begin
    bit2 <= 1'b0;
  end else
  if (~n_t_37x) begin
    bit2 <= 1'b1;
  end else
  if (n_t_16x) begin
    bit2 <= bit2_m;
  end
always @(n_t_16x, ioclr_l, n_t_52x, bit4)
  if (~ioclr_l) begin
    bit3_m <= 1'b0;
  end else
  if (~n_t_52x) begin
    bit3_m <= 1'b1;
  end else
  if (~(n_t_16x)) begin
    bit3_m <= bit4;
  end
always @(n_t_16x, ioclr_l, n_t_52x, bit3_m)
  if (~ioclr_l) begin
    bit3 <= 1'b0;
  end else
  if (~n_t_52x) begin
    bit3 <= 1'b1;
  end else
  if (n_t_16x) begin
    bit3 <= bit3_m;
  end
// e16: sn7474 
always @(n2xclk, ioclr_l, n3v, n_t_28x)
  if (~ioclr_l) begin
    active_m <= 1'b0;
  end else
  if (~n3v) begin
    active_m <= 1'b1;
  end else
  if (~(n2xclk)) begin
    active_m <= n_t_28x;
  end
always @(n2xclk, ioclr_l, n3v, active_m)
  if (~ioclr_l) begin
    active <= 1'b0;
  end else
  if (~n3v) begin
    active <= 1'b1;
  end else
  if (n2xclk) begin
    active <= active_m;
  end
always @(n_t_16x, n3v, n_t_35x, n_t_6x)
  if (~n3v) begin
    irq_m <= 1'b0;
  end else
  if (n_t_35x) begin
    irq_m <= 1'b1;
  end else
  if (~(n_t_16x)) begin
    irq_m <= n_t_6x;
  end
always @(n_t_16x, n3v, n_t_35x, irq_m)
  if (~n3v) begin
    irq <= 1'b0;
  end else
  if (n_t_35x) begin
    irq <= 1'b1;
  end else
  if (n_t_16x) begin
    irq <= irq_m;
  end
// e17: sn7474 
always @(n2xclk, n_t_16x, n3v, n_t_138x)
  if (~n_t_16x) begin
    bn1_m <= 1'b0;
  end else
  if (~n3v) begin
    bn1_m <= 1'b1;
  end else
  if (~(n2xclk)) begin
    bn1_m <= ~n_t_138x;
  end
always @(n2xclk, n_t_16x, n3v, bn1_m)
  if (~n_t_16x) begin
    bn1 <= 1'b0;
  end else
  if (~n3v) begin
    bn1 <= 1'b1;
  end else
  if (n2xclk) begin
    bn1 <= bn1_m;
  end
always @(n2xclk, n3v, n_t_16x, n_t_166x)
  if (~n3v) begin
    n_t_138x_m <= 1'b0;
  end else
  if (~n_t_16x) begin
    n_t_138x_m <= 1'b1;
  end else
  if (~(n2xclk)) begin
    n_t_138x_m <= n_t_166x;
  end
always @(n2xclk, n3v, n_t_16x, n_t_138x_m)
  if (~n3v) begin
    n_t_138x <= 1'b0;
  end else
  if (~n_t_16x) begin
    n_t_138x <= 1'b1;
  end else
  if (n2xclk) begin
    n_t_138x <= n_t_138x_m;
  end
assign bp1 = ~n_t_138x;
// e18: sn7400 
assign n_t_10x = ~(n_t_39x & active);
assign n_t_11x = ~(active & n_t_16x);
assign n_t_161x = ~(wait_l & ~active);
assign n_t_62x = ~(stop & size);
// open collector 'wire-or's 
endmodule