~/Verilog/bin/topld.pl M708B
info: 7400n ne dil14
info: 7400n ne dil14
info: 7430n ne dil14
info: 7400n ne dil14
info: 7400n ne dil14
info: single ne edge_con2
warning: making u$1/single/ a connector
~/Verilog/bin/smaller.pl M708B.PLD >vv || (rm vv; exit 1)
4 signals were removed:
  n_t_26x: !clock_iot
  n_t_32x: !n_t_31x
  n_t_35x: !load_counter
  n_t_41x: !n_t_40x
~/Verilog/bin/smaller.pl vv >M708BX.PLD || (rm M708BX.PLD; exit 1)
0 signals were removed:
~/Verilog/bin/cupl2v.pl M708BX.PLD >vv || (rm vv; exit 1)
mv vv M708B.v
rm M708BX.PLD