// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// c5: c_us 
// c6: c_us 
// c7: c_us 
// c8: c_us 
// c9: c_us 
// e1: sn7401 
// io_irq_l = !(flag & irq_enb); 
// io_skip_l = !(flag_buffer & !n_t_31x); 
// clr_flag_l = !(!n_t_31x & flag_buffer); 
// clr_flag_l = !n_t_14x; 
// e2: sn7474 
module m708x (n3v1, clock, clock_enable, clock_iot, clr_flag_l, flag, flag_buffer, initialize, io_irq_l, io_skip_l, iop1_l, iop2_l, iop4, iop4_l, irq_enb, load_counter, mb10, mb11, mb3_l, mb4_l, mb5, mb6_l, mb7, mb8, mb9, mb9_l, overflow);
input n3v1;
input clock;
output clock_enable;
inout clock_iot;
inout clr_flag_l;
inout reg flag;
inout reg flag_buffer;
input initialize;
output io_irq_l;
output io_skip_l;
input iop1_l;
input iop2_l;
output iop4;
input iop4_l;
inout reg irq_enb;
inout load_counter;
input mb10;
input mb11;
input mb3_l;
input mb4_l;
input mb5;
input mb6_l;
input mb7;
input mb8;
input mb9;
input mb9_l;
input overflow;

reg flag_m;
reg flag_buffer_m;
reg irq_enb_m;
reg n_t_36x_m;

reg n_t_36x;
wire iop1;
wire iop2;
wire n_t_14x;
wire n_t_29x;
wire n_t_31x;
wire n_t_34x;
wire n_t_37x;
wire n_t_38x;
wire n_t_40x;
always @(n_t_31x, n_t_29x, flag)
  if (~n_t_29x) begin
    flag_buffer_m <= 1'b0;
  end else
  if (~(~n_t_31x)) begin
    flag_buffer_m <= flag;
  end
always @(n_t_31x, n_t_29x, flag_buffer_m)
  if (~n_t_29x) begin
    flag_buffer <= 1'b0;
  end else
  if (~n_t_31x) begin
    flag_buffer <= flag_buffer_m;
  end
always @(clock, clr_flag_l, n_t_40x)
  if (~clr_flag_l) begin
    flag_m <= 1'b0;
  end else
  if (~(clock)) begin
    flag_m <= ~n_t_40x;
  end
always @(clock, clr_flag_l, flag_m)
  if (~clr_flag_l) begin
    flag <= 1'b0;
  end else
  if (clock) begin
    flag <= flag_m;
  end
// e3: sn7474 
always @(n_t_14x, n_t_37x, 1'b0)
  if (~n_t_37x) begin
    n_t_36x_m <= 1'b1;
  end else
  if (~(n_t_14x)) begin
    n_t_36x_m <= 1'b0;
  end
always @(n_t_14x, n_t_37x, n_t_36x_m)
  if (~n_t_37x) begin
    n_t_36x <= 1'b1;
  end else
  if (n_t_14x) begin
    n_t_36x <= n_t_36x_m;
  end
assign clock_enable = ~n_t_36x;
always @(n_t_14x, n_t_38x, 1'b0)
  if (~n_t_38x) begin
    irq_enb_m <= 1'b1;
  end else
  if (~(n_t_14x)) begin
    irq_enb_m <= 1'b0;
  end
always @(n_t_14x, n_t_38x, irq_enb_m)
  if (~n_t_38x) begin
    irq_enb <= 1'b1;
  end else
  if (n_t_14x) begin
    irq_enb <= irq_enb_m;
  end
// e4: sn7400 
assign n_t_38x = ~(mb11 & load_counter);
assign n_t_40x = ~(n_t_36x & overflow);
// e5: sn7400 
assign iop1 = ~(iop1_l & n3v1);
assign iop4 = ~(iop4_l & n3v1);
// e6: sn7430 
assign clock_iot = ~(~(mb3_l & mb4_l & mb5 & mb6_l & mb7 & mb8 & n3v1 & n3v1));
// e7: sn7400 
assign n_t_29x = ~(clock_iot & iop2);
assign iop2 = ~(n3v1 & iop2_l);
assign n_t_34x = ~(mb9_l & mb11);
// e8: sn7420 
assign n_t_31x = ~(clock_iot & iop1 & mb10 & mb9_l);
assign load_counter = ~(~(n_t_34x & clock_iot & iop2));
// e9: sn7400 
assign n_t_37x = ~(load_counter & mb9);
assign n_t_14x = ~(~load_counter & initialize);
// open collector 'wire-or's 
assign clr_flag_l = (~n_t_31x & flag_buffer)
                     | n_t_14x? 1'b0: 1'bz;
assign io_irq_l = (flag & irq_enb)? 1'b0: 1'bz;
assign io_skip_l = (flag_buffer & ~n_t_31x)? 1'b0: 1'bz;
endmodule