// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// c5: c_us 
// c6: c_us 
// c7: c_us 
// c8: c_us 
// c9: c_us 
// c10: c_us 
// c11: c_us 
// c12: c_us 
// c13: c_us 
// c14: c_us 
// c15: c_us 
// c16: c_us 
// c17: c_us 
// c18: c_us 
// c19: c_us 
// c20: c_us 
// c21: c_us 
// c22: c_us 
// c23: c_us 
// c24: cpol_use 
// c25: cpol_use 
// c26: c_us 
// c27: c_us 
// e1: sn7474 
module m709b (n_t_84x, n_t_86x, clk_cla, clk_count, clock, clock_iop4, clock_iot, gate, load_counter, mb10, mb10_l, n_t_13x, n_t_14x, n_t_15x, n_t_16x, n_t_17x, n_t_18x, n_t_19x, n_t_20x, n_t_21x, n_t_22x, n_t_23x, n_t_24x, n_t_25x, n_t_27x, n_t_60x, n_t_69x, n_t_70x, n_t_71x, n_t_72x, n_t_73x, n_t_74x, n_t_75x, n_t_76x, n_t_77x, n_t_78x, n_t_79x, n_t_87x, n_t_89x, overflow, set_count, transfer);
input n_t_84x;
input n_t_86x;
inout clk_cla;
inout clk_count;
input clock;
input clock_iop4;
input clock_iot;
inout reg gate;
input load_counter;
input mb10;
input mb10_l;
inout n_t_13x;
output n_t_14x;
output n_t_15x;
output n_t_16x;
output n_t_17x;
output n_t_18x;
output n_t_19x;
output n_t_20x;
output n_t_21x;
output n_t_22x;
output n_t_23x;
output n_t_24x;
output n_t_25x;
inout n_t_27x;
input n_t_60x;
input n_t_69x;
input n_t_70x;
input n_t_71x;
input n_t_72x;
input n_t_73x;
input n_t_74x;
input n_t_75x;
input n_t_76x;
input n_t_77x;
input n_t_78x;
input n_t_79x;
output n_t_87x;
inout n_t_89x;
inout reg overflow;
inout set_count;
inout transfer;

reg gate_m;
reg n_t_28x_m;
reg n_t_29x_m;
reg n_t_30x_m;
reg n_t_31x_m;
reg n_t_32x_m;
reg n_t_33x_m;
reg n_t_34x_m;
reg n_t_35x_m;
reg n_t_36x_m;
reg n_t_37x_m;
reg n_t_38x_m;
reg n_t_39x_m;
reg overflow_m;

reg n_t_2x;
reg n_t_1x;
reg n_t_4x;
reg n_t_3x;
reg n_t_7x;
reg n_t_6x;
reg n_t_8x;
reg n_t_9x;
reg n_t_10x;
reg n_t_11x;
reg n_t_5x;
reg n_t_12x;
reg n_t_38x;
reg n_t_39x;
reg n_t_36x;
reg n_t_37x;
reg n_t_34x;
reg n_t_35x;
reg n_t_32x;
reg n_t_33x;
reg n_t_30x;
reg n_t_31x;
reg n_t_28x;
reg n_t_29x;
wire n_t_53x;
wire n_t_54x;
wire n_t_55x;
wire n_t_56x;
wire n_t_59x;
wire n_t_61x;
wire n_t_62x;
wire n_t_63x;
wire n_t_64x;
wire n_t_65x;
wire n_t_66x;
wire n_t_67x;
wire n_t_68x;
wire n_t_81x;
wire n_t_85x;
always @(posedge transfer)
  if (transfer) begin
    n_t_2x <= n_t_38x;
  end
always @(posedge transfer)
  if (transfer) begin
    n_t_1x <= n_t_39x;
  end
// e2: sn7474 
always @(posedge transfer)
  if (transfer) begin
    n_t_4x <= n_t_36x;
  end
always @(posedge transfer)
  if (transfer) begin
    n_t_3x <= n_t_37x;
  end
// e3: sn7474 
always @(posedge transfer)
  if (transfer) begin
    n_t_7x <= n_t_34x;
  end
always @(posedge transfer)
  if (transfer) begin
    n_t_6x <= n_t_35x;
  end
// e4: sn7474 
always @(posedge transfer)
  if (transfer) begin
    n_t_8x <= n_t_32x;
  end
always @(posedge transfer)
  if (transfer) begin
    n_t_9x <= n_t_33x;
  end
// e5: sn7474 
always @(posedge transfer)
  if (transfer) begin
    n_t_10x <= n_t_30x;
  end
always @(posedge transfer)
  if (transfer) begin
    n_t_11x <= n_t_31x;
  end
// e6: sn7474 
always @(posedge transfer)
  if (transfer) begin
    n_t_5x <= n_t_28x;
  end
always @(posedge transfer)
  if (transfer) begin
    n_t_12x <= n_t_29x;
  end
// e7: sn7400 
assign n_t_54x = ~(n_t_70x & ~gate);
assign n_t_53x = ~(~gate & n_t_71x);
assign n_t_55x = ~(n_t_69x & ~gate);
assign n_t_56x = ~(~gate & n_t_60x);
// e8: sn7401 
// n_t_14x = !(n_t_4x & n_t_27x); 
// n_t_15x = !(n_t_27x & n_t_3x); 
// n_t_17x = !(n_t_27x & n_t_1x); 
// n_t_16x = !(n_t_27x & n_t_2x); 
// e9: sn7400 
assign n_t_62x = ~(n_t_73x & ~gate);
assign n_t_61x = ~(~gate & n_t_77x);
assign n_t_63x = ~(n_t_74x & ~gate);
assign n_t_64x = ~(~gate & n_t_72x);
// e10: sn7401 
// n_t_20x = !(n_t_8x & n_t_13x); 
// n_t_19x = !(n_t_13x & n_t_9x); 
// n_t_21x = !(n_t_27x & n_t_6x); 
// n_t_18x = !(n_t_27x & n_t_7x); 
// e11: sn7400 
assign n_t_68x = ~(n_t_78x & ~gate);
assign n_t_67x = ~(~gate & n_t_79x);
assign n_t_66x = ~(n_t_75x & ~gate);
assign n_t_65x = ~(~gate & n_t_76x);
// e12: sn7401 
// n_t_22x = !(n_t_5x & n_t_13x); 
// n_t_23x = !(n_t_13x & n_t_12x); 
// n_t_25x = !(n_t_13x & n_t_11x); 
// n_t_24x = !(n_t_13x & n_t_10x); 
// e13: sn7474 
always @(n_t_39x, n_t_55x, set_count, n_t_38x)
  if (~n_t_55x) begin
    n_t_38x_m <= 1'b0;
  end else
  if (~set_count) begin
    n_t_38x_m <= 1'b1;
  end else
  if (~(~n_t_39x)) begin
    n_t_38x_m <= ~n_t_38x;
  end
always @(n_t_39x, n_t_55x, set_count, n_t_38x_m)
  if (~n_t_55x) begin
    n_t_38x <= 1'b0;
  end else
  if (~set_count) begin
    n_t_38x <= 1'b1;
  end else
  if (~n_t_39x) begin
    n_t_38x <= n_t_38x_m;
  end
always @(clk_count, n_t_56x, set_count, n_t_39x)
  if (~n_t_56x) begin
    n_t_39x_m <= 1'b0;
  end else
  if (~set_count) begin
    n_t_39x_m <= 1'b1;
  end else
  if (~(clk_count)) begin
    n_t_39x_m <= ~n_t_39x;
  end
always @(clk_count, n_t_56x, set_count, n_t_39x_m)
  if (~n_t_56x) begin
    n_t_39x <= 1'b0;
  end else
  if (~set_count) begin
    n_t_39x <= 1'b1;
  end else
  if (clk_count) begin
    n_t_39x <= n_t_39x_m;
  end
// e14: sn7474 
always @(n_t_37x, n_t_53x, set_count, n_t_36x)
  if (~n_t_53x) begin
    n_t_36x_m <= 1'b0;
  end else
  if (~set_count) begin
    n_t_36x_m <= 1'b1;
  end else
  if (~(~n_t_37x)) begin
    n_t_36x_m <= ~n_t_36x;
  end
always @(n_t_37x, n_t_53x, set_count, n_t_36x_m)
  if (~n_t_53x) begin
    n_t_36x <= 1'b0;
  end else
  if (~set_count) begin
    n_t_36x <= 1'b1;
  end else
  if (~n_t_37x) begin
    n_t_36x <= n_t_36x_m;
  end
always @(n_t_38x, n_t_54x, set_count, n_t_37x)
  if (~n_t_54x) begin
    n_t_37x_m <= 1'b0;
  end else
  if (~set_count) begin
    n_t_37x_m <= 1'b1;
  end else
  if (~(~n_t_38x)) begin
    n_t_37x_m <= ~n_t_37x;
  end
always @(n_t_38x, n_t_54x, set_count, n_t_37x_m)
  if (~n_t_54x) begin
    n_t_37x <= 1'b0;
  end else
  if (~set_count) begin
    n_t_37x <= 1'b1;
  end else
  if (~n_t_38x) begin
    n_t_37x <= n_t_37x_m;
  end
// e15: sn7474 
always @(n_t_35x, n_t_63x, set_count, n_t_34x)
  if (~n_t_63x) begin
    n_t_34x_m <= 1'b0;
  end else
  if (~set_count) begin
    n_t_34x_m <= 1'b1;
  end else
  if (~(~n_t_35x)) begin
    n_t_34x_m <= ~n_t_34x;
  end
always @(n_t_35x, n_t_63x, set_count, n_t_34x_m)
  if (~n_t_63x) begin
    n_t_34x <= 1'b0;
  end else
  if (~set_count) begin
    n_t_34x <= 1'b1;
  end else
  if (~n_t_35x) begin
    n_t_34x <= n_t_34x_m;
  end
always @(n_t_36x, n_t_64x, set_count, n_t_35x)
  if (~n_t_64x) begin
    n_t_35x_m <= 1'b0;
  end else
  if (~set_count) begin
    n_t_35x_m <= 1'b1;
  end else
  if (~(~n_t_36x)) begin
    n_t_35x_m <= ~n_t_35x;
  end
always @(n_t_36x, n_t_64x, set_count, n_t_35x_m)
  if (~n_t_64x) begin
    n_t_35x <= 1'b0;
  end else
  if (~set_count) begin
    n_t_35x <= 1'b1;
  end else
  if (~n_t_36x) begin
    n_t_35x <= n_t_35x_m;
  end
// e16: sn7474 
always @(n_t_33x, n_t_61x, set_count, n_t_32x)
  if (~n_t_61x) begin
    n_t_32x_m <= 1'b0;
  end else
  if (~set_count) begin
    n_t_32x_m <= 1'b1;
  end else
  if (~(~n_t_33x)) begin
    n_t_32x_m <= ~n_t_32x;
  end
always @(n_t_33x, n_t_61x, set_count, n_t_32x_m)
  if (~n_t_61x) begin
    n_t_32x <= 1'b0;
  end else
  if (~set_count) begin
    n_t_32x <= 1'b1;
  end else
  if (~n_t_33x) begin
    n_t_32x <= n_t_32x_m;
  end
always @(n_t_34x, n_t_62x, set_count, n_t_33x)
  if (~n_t_62x) begin
    n_t_33x_m <= 1'b0;
  end else
  if (~set_count) begin
    n_t_33x_m <= 1'b1;
  end else
  if (~(~n_t_34x)) begin
    n_t_33x_m <= ~n_t_33x;
  end
always @(n_t_34x, n_t_62x, set_count, n_t_33x_m)
  if (~n_t_62x) begin
    n_t_33x <= 1'b0;
  end else
  if (~set_count) begin
    n_t_33x <= 1'b1;
  end else
  if (~n_t_34x) begin
    n_t_33x <= n_t_33x_m;
  end
// e17: sn7474 
always @(n_t_31x, n_t_66x, set_count, n_t_30x)
  if (~n_t_66x) begin
    n_t_30x_m <= 1'b0;
  end else
  if (~set_count) begin
    n_t_30x_m <= 1'b1;
  end else
  if (~(~n_t_31x)) begin
    n_t_30x_m <= ~n_t_30x;
  end
always @(n_t_31x, n_t_66x, set_count, n_t_30x_m)
  if (~n_t_66x) begin
    n_t_30x <= 1'b0;
  end else
  if (~set_count) begin
    n_t_30x <= 1'b1;
  end else
  if (~n_t_31x) begin
    n_t_30x <= n_t_30x_m;
  end
always @(n_t_32x, n_t_65x, set_count, n_t_31x)
  if (~n_t_65x) begin
    n_t_31x_m <= 1'b0;
  end else
  if (~set_count) begin
    n_t_31x_m <= 1'b1;
  end else
  if (~(~n_t_32x)) begin
    n_t_31x_m <= ~n_t_31x;
  end
always @(n_t_32x, n_t_65x, set_count, n_t_31x_m)
  if (~n_t_65x) begin
    n_t_31x <= 1'b0;
  end else
  if (~set_count) begin
    n_t_31x <= 1'b1;
  end else
  if (~n_t_32x) begin
    n_t_31x <= n_t_31x_m;
  end
// e18: sn7474 
always @(n_t_29x, n_t_68x, set_count, n_t_28x)
  if (~n_t_68x) begin
    n_t_28x_m <= 1'b0;
  end else
  if (~set_count) begin
    n_t_28x_m <= 1'b1;
  end else
  if (~(~n_t_29x)) begin
    n_t_28x_m <= ~n_t_28x;
  end
always @(n_t_29x, n_t_68x, set_count, n_t_28x_m)
  if (~n_t_68x) begin
    n_t_28x <= 1'b0;
  end else
  if (~set_count) begin
    n_t_28x <= 1'b1;
  end else
  if (~n_t_29x) begin
    n_t_28x <= n_t_28x_m;
  end
always @(n_t_30x, n_t_67x, set_count, n_t_29x)
  if (~n_t_67x) begin
    n_t_29x_m <= 1'b0;
  end else
  if (~set_count) begin
    n_t_29x_m <= 1'b1;
  end else
  if (~(~n_t_30x)) begin
    n_t_29x_m <= ~n_t_29x;
  end
always @(n_t_30x, n_t_67x, set_count, n_t_29x_m)
  if (~n_t_67x) begin
    n_t_29x <= 1'b0;
  end else
  if (~set_count) begin
    n_t_29x <= 1'b1;
  end else
  if (~n_t_30x) begin
    n_t_29x <= n_t_29x_m;
  end
// e19: sn7440 
assign set_count = ~load_counter;
assign transfer = ~n_t_86x;
// e20: sn7400 
assign n_t_27x = ~clk_cla;
assign n_t_13x = ~clk_cla;
assign n_t_89x = ~n_t_84x;
assign n_t_87x = ~(n_t_89x & n_t_85x);
// e21: sn7410 
assign n_t_81x = ~(mb10 & clock_iop4 & clock_iot);
assign n_t_85x = ~(~clk_count & clk_cla & clk_cla);
assign clk_cla = ~(mb10_l & clock_iop4 & clock_iot);
// e22: sn7400 
assign n_t_59x = ~(gate & clock);
assign clk_count = ~(~(n_t_81x & n_t_59x));
// e23: sn7474 
always @(n_t_28x, gate, overflow)
  if (~gate) begin
    overflow_m <= 1'b0;
  end else
  if (~(~n_t_28x)) begin
    overflow_m <= ~overflow;
  end
always @(n_t_28x, gate, overflow_m)
  if (~gate) begin
    overflow <= 1'b0;
  end else
  if (~n_t_28x) begin
    overflow <= overflow_m;
  end
always @(set_count, n_t_81x, 1'b0)
  if (~set_count) begin
    gate_m <= 1'b0;
  end else
  if (~n_t_81x) begin
    gate_m <= 1'b1;
  end else
  if (~(1'b0)) begin
    gate_m <= 1'b0;
  end
always @(set_count, n_t_81x, gate_m)
  if (~set_count) begin
    gate <= 1'b0;
  end else
  if (~n_t_81x) begin
    gate <= 1'b1;
  end else
  if (1'b0) begin
    gate <= gate_m;
  end
// open collector 'wire-or's 
assign n_t_14x = (n_t_4x & n_t_27x)? 1'b0: 1'bz;
assign n_t_15x = (n_t_27x & n_t_3x)? 1'b0: 1'bz;
assign n_t_16x = (n_t_27x & n_t_2x)? 1'b0: 1'bz;
assign n_t_17x = (n_t_27x & n_t_1x)? 1'b0: 1'bz;
assign n_t_18x = (n_t_27x & n_t_7x)? 1'b0: 1'bz;
assign n_t_19x = (n_t_13x & n_t_9x)? 1'b0: 1'bz;
assign n_t_20x = (n_t_8x & n_t_13x)? 1'b0: 1'bz;
assign n_t_21x = (n_t_27x & n_t_6x)? 1'b0: 1'bz;
assign n_t_22x = (n_t_5x & n_t_13x)? 1'b0: 1'bz;
assign n_t_23x = (n_t_13x & n_t_12x)? 1'b0: 1'bz;
assign n_t_24x = (n_t_13x & n_t_10x)? 1'b0: 1'bz;
assign n_t_25x = (n_t_13x & n_t_11x)? 1'b0: 1'bz;
endmodule