/* This file is generated by topld.pl!! */ /* Please don't edit it. */ Name M7104B ; PartNo cpld ; Date XX/XX/XXXX ; Revision 01 ; Designer ; Company ; Assembly None ; Location E1 ; Device f1508isptqfp100; $DEFINE OPTIMIZE $UNDEF OPTIMIZE /* Input Pins */ pin = bdata1; pin = bdata10; pin = bdata10_l; pin = bdata11; pin = bdata11_l; pin = brk_dir_l; pin = brk_rq; pin = data_clk_ok; pin = data_enable; pin = data_state; pin = data_state_l; pin = db_cont4_l; pin = drive_status_bad; pin = drv_revo; pin = dsk_capacity_ex_l; pin = dsk_file_rdy_l; pin = dsk_wrt_status_l; pin = enab_int; pin = enab_seek_done; pin = end_state_l; pin = hi_data_in; pin = hi_rd_clk; pin = idle; pin = idle_l; pin = last_word_pl; pin = ld_cmd_reg; pin = ld_disk_addrs; pin = lo_main_data; pin = lo_main_shft_l; pin = main; pin = main_l; pin = main_pl; pin = mak_l; pin = n12th_bit_ok; pin = n_t_102x; pin = n_t_10x; pin = n_t_20x; pin = n_t_24x; pin = n_t_25x; pin = n_t_27x; pin = n_t_6x; pin = n_t_74x; pin = n_t_75x; pin = n_t_76x; pin = n_t_8x; pin = not_equal_l; pin = rd_brk_l; pin = rdy_s_r_w_l; pin = rdy_s_r_w_slo; pin = sector_seek_l; pin = seek_fail; pin = shft_wrt_buff_l; pin = write; pin = wrt_brk_l; pin = wrt_cmd_l; pin = wt_buff_data_l; /* Output Pins */ pin = ac7_l; pin = b_brk_rq; pin = bmd6; pin = bmd7; pin = bmd8; pin = btp2; pin = btp3; pin = btp3_l; pin = btp3_ok; pin = busy_error; pin = c0_l; pin = c1_l; pin = clr_all; pin = clr_all_l; pin = clr_drive_cmd_l; pin = crc_error; pin = data0_l; pin = data10_l; pin = data11_l; pin = data1_l; pin = data2_l; pin = data3_l; pin = data4_l; pin = data5_l; pin = data6_l; pin = data7_l; pin = data8_l; pin = data9_l; pin = db_clk; pin = db_cont1_l; pin = db_cont2; pin = db_cont4; pin = device_rk; pin = error_clr_l; pin = initialize; pin = int_rqst_l; pin = internal_io_l; pin = io_pause_l; pin = md0_l; pin = md10_l; pin = md11_l; pin = md1_l; pin = md2_l; pin = md3_l; pin = md4_l; pin = md5_l; pin = md6_l; pin = md7_l; pin = md8_l; pin = md9_l; pin = md_rd_buff_l; pin = md_rk_l; pin = n3v; pin = n6rk2_l; pin = n6rk3_ok; pin = n6rk3_ok_l; pin = n6rk4_l; pin = n6rk6; pin = n6rk7; pin = n6rk7_ok; pin = n_t_101x; pin = n_t_1x; pin = n_t_22x; pin = n_t_5x; pin = n_t_82x; pin = n_t_93x; pin = power_ok; pin = rk_data11; pin = set_idle_pl_l; pin = skip_l; pin = test_clk; pin = test_clk_l; pin = tp1; pin = tp2; pin = tp3; pin = ts3_l; node n_t_18x; node n_t_23x; node n_t_26x; node n_t_28x; node n_t_45x; node n_t_46x; node n_t_47x; node n_t_48x; node n_t_49x; node n_t_50x; node n_t_63x; node n_t_62x; node n_t_37x; node n_t_38x; node rk_data0; node rk_data1; node rk_data2; node rk_data3; node n_t_67x; node n_t_66x; node n_t_65x; node n_t_61x; node n_t_60x; node n_t_40x; node db_cont1; node db_cont3; node rk_data4; node rk_data5; node rk_data6; node rk_data7; node n_t_36x; node n_t_39x; node n_t_44x; node n_t_57x; node n_t_58x; node n_t_59x; node rk_data8; node rk_data9; node rk_data10; node n_t_51x; node n_t_52x; node n_t_53x; node n_t_54x; node n_t_55x; node n_t_56x; node n_t_32x; node n_t_31x; node n_t_30x; node n_t_64x; node ac7; node data_rqst_late; node done_flag_l; node gdollar_4; node gdollar_5; node gdollar_6; node set_time_out_er; node time_out_er; node drive_status_er; node cyl_addrs_er; node wrt_lock_er; node clr_syn_l; /* Internal nodes */ $IFNDEF OPTIMIZE node b_drive_status_er; node b_io_pause; node b_io_pause_l; node bmd0; node bmd1; node bmd10; node bmd11; node bmd2; node bmd3; node bmd4; node bmd5; node bmd9; node btp1; node btp3_ok_l; node clr_status_l; node data_rqst_late_l; node db4_ena; node db_cont2_l; node db_cont3_l; node device_rk_l; node done_flag; node enab_rk_data; node enab_rk_data_l; node enable_status; node error_fl_l; node hi_rd_clk_l; node hi_wrt_clk; node ld_db4; node ld_db_ac; node ld_db_ac_l; node ld_rd_buffer; node md_rd_buff; node n0_db4; node n1_db2; node n1_db3; node n1_db4; node n6rk1; node n6rk1_l; node n6rk2; node n6rk3_l; node n6rk5_l; node n6rk6_l; node n6rk7_l; node n_t_100x; node n_t_12x; node n_t_13x; node n_t_14x; node n_t_15x; node n_t_16x; node n_t_17x; node n_t_19x; node n_t_34x; node n_t_35x; node n_t_3x; node n_t_41x; node n_t_42x; node n_t_43x; node n_t_68x; node n_t_70x; node n_t_71x; node n_t_72x; node n_t_73x; node n_t_77x; node n_t_78x; node n_t_79x; node n_t_7x; node n_t_80x; node n_t_81x; node n_t_83x; node n_t_84x; node n_t_85x; node n_t_86x; node n_t_87x; node n_t_88x; node n_t_89x; node n_t_90x; node n_t_95x; node n_t_97x; node n_t_98x; node n_t_99x; node rk_data0_l; node rk_data10_l; node rk_data11_l; node rk_data1_l; node rk_data2_l; node rk_data3_l; node rk_data4_l; node rk_data5_l; node rk_data6_l; node rk_data7_l; node rk_data8_l; node rk_data9_l; node set_busy_er; node set_crc_er; node set_cyl_addrs_er; node set_status_er; node short_tp3; node wrt_buf_data; node wrt_buff_shft; node wrt_buff_shft_l; node wrt_lock_er_l; $ENDIF /* Code nodes */ /* Equations */ /* c1: c_us */ /* c2: c_us */ /* c3: c_us */ /* c4: c_us */ /* c5: c_us */ /* c6: c_us */ /* c7: c_us */ /* c8: c_us */ /* c9: c_us */ /* c10: c_us */ /* c11: c_us */ /* c12: c_us */ /* c13: c_us */ /* c14: c_us */ /* c15: c_us */ /* c16: c_us */ /* c17: c_us */ /* c18: c_us */ /* c19: c_us */ /* c20: c_us */ /* c21: c_us */ /* c22: c_us */ /* c23: c_us */ /* c24: c_us */ /* c25: c_us */ /* c26: c_us */ /* c27: c_us */ /* c28: c_us */ /* c29: c_us */ /* c30: c_us */ /* c31: c_us */ /* c32: c_us */ /* c33: c_us */ /* c34: c_us */ /* c35: c_us */ /* c36: c_us */ /* c37: c_us */ /* c38: c_us */ /* c39: c_us */ /* c40: c_us */ /* c41: c_us */ /* c42: c_us */ /* c43: c_us */ /* c44: c_us */ /* c45: c_us */ /* c46: c_us */ /* c47: c_us */ /* c48: c_us */ /* c49: c_us */ /* c50: c_us */ /* c51: c_us */ /* c52: c_us */ /* c53: cpol_use */ /* c54: cpol_use */ /* c55: cpol_use */ /* c56: c_us */ /* e1: sp314n */ !device_rk = n_t_74x # n_t_75x # n_t_76x # md5_l # md4_l # b_io_pause_l # md3_l; /* e2: ds8640n */ bmd2 = !(md2_l # md_rd_buff_l); bmd0 = !(md_rd_buff_l # md0_l); bmd1 = !(md1_l # md_rd_buff_l); bmd3 = !(md_rd_buff_l # md3_l); /* e3: sn7495 */ n_t_18x.ck = !(hi_wrt_clk & !md_rd_buff # ld_rd_buffer & md_rd_buff); n_t_18x.d = bmd0 & md_rd_buff # hi_data_in & !md_rd_buff; n_t_23x.ck = !(hi_wrt_clk & !md_rd_buff # ld_rd_buffer & md_rd_buff); n_t_23x.d = bmd1 & md_rd_buff # n_t_18x & !md_rd_buff; n_t_26x.ck = !(hi_wrt_clk & !md_rd_buff # ld_rd_buffer & md_rd_buff); n_t_26x.d = bmd2 & md_rd_buff # n_t_23x & !md_rd_buff; n_t_28x.ck = !(hi_wrt_clk & !md_rd_buff # ld_rd_buffer & md_rd_buff); n_t_28x.d = bmd3 & md_rd_buff # n_t_26x & !md_rd_buff; /* e4: sn74174 */ n_t_45x.ar = !n3v; n_t_45x.ck = db_cont2; n_t_45x.d = n_t_18x; n_t_46x.ar = !n3v; n_t_46x.ck = db_cont2; n_t_46x.d = n_t_23x; n_t_47x.ar = !n3v; n_t_47x.ck = db_cont2; n_t_47x.d = n_t_26x; n_t_48x.ar = !n3v; n_t_48x.ck = db_cont2; n_t_48x.d = n_t_28x; n_t_49x.ar = !n3v; n_t_49x.ck = db_cont2; n_t_49x.d = n_t_63x; n_t_50x.ar = !n3v; n_t_50x.ck = db_cont2; n_t_50x.d = n_t_62x; /* e5: sn7495 */ n_t_63x.ck = !(hi_wrt_clk & !md_rd_buff # ld_rd_buffer & md_rd_buff); n_t_63x.d = bmd4 & md_rd_buff # n_t_28x & !md_rd_buff; n_t_62x.ck = !(hi_wrt_clk & !md_rd_buff # ld_rd_buffer & md_rd_buff); n_t_62x.d = bmd5 & md_rd_buff # n_t_63x & !md_rd_buff; n_t_37x.ck = !(hi_wrt_clk & !md_rd_buff # ld_rd_buffer & md_rd_buff); n_t_37x.d = bmd6 & md_rd_buff # n_t_62x & !md_rd_buff; n_t_38x.ck = !(hi_wrt_clk & !md_rd_buff # ld_rd_buffer & md_rd_buff); n_t_38x.d = bmd7 & md_rd_buff # n_t_37x & !md_rd_buff; /* e6: sn74h53 */ /* gdollar_0 = !(n1_db2 # db4_ena & n1_db4 # n0_db4 # n1_db3); */ /* gdollar_1 = !gdollar_0; */ n_t_22x = gdollar_0; /* e8: dec8235 */ /* data0_l = !(!rk_data0_l & !enab_rk_data_l # done_flag & !n6rk5_l); */ /* data1_l = !(!rk_data1_l & !enab_rk_data_l # rdy_s_r_w_l & !n6rk5_l); */ /* data2_l = !(!rk_data2_l & !enab_rk_data_l); */ /* data3_l = !(!rk_data3_l & !enab_rk_data_l # seek_fail & !n6rk5_l); */ /* e9: sn7495 */ rk_data0.ck = !(wrt_buff_shft_l & !db_cont4_l # ld_db4 & db_cont4_l); rk_data0.d = n_t_67x & db_cont4_l # lo_main_data & !db_cont4_l; rk_data1.ck = !(wrt_buff_shft_l & !db_cont4_l # ld_db4 & db_cont4_l); rk_data1.d = n_t_66x & db_cont4_l # rk_data0 & !db_cont4_l; rk_data2.ck = !(wrt_buff_shft_l & !db_cont4_l # ld_db4 & db_cont4_l); rk_data2.d = n_t_65x & db_cont4_l # rk_data1 & !db_cont4_l; rk_data3.ck = !(wrt_buff_shft_l & !db_cont4_l # ld_db4 & db_cont4_l); rk_data3.d = n_t_61x & db_cont4_l # rk_data2 & !db_cont4_l; /* e10: sn74174 */ n_t_67x.ar = !n3v; n_t_67x.ck = db_cont3; n_t_67x.d = n_t_45x; n_t_66x.ar = !n3v; n_t_66x.ck = db_cont3; n_t_66x.d = n_t_46x; n_t_65x.ar = !n3v; n_t_65x.ck = db_cont3; n_t_65x.d = n_t_47x; n_t_61x.ar = !n3v; n_t_61x.ck = db_cont3; n_t_61x.d = n_t_48x; n_t_60x.ar = !n3v; n_t_60x.ck = db_cont3; n_t_60x.d = n_t_49x; n_t_40x.ar = !n3v; n_t_40x.ck = db_cont3; n_t_40x.d = n_t_50x; /* e11: sn7408 */ n_t_13x = (n12th_bit_ok & wrt_cmd_l); n_t_16x = (n1_db2 & db_cont2); ld_db4 = (n1_db4 & db_clk); hi_wrt_clk = (hi_rd_clk_l & wrt_cmd_l); /* e12: sn7473 */ db_cont1.ar = !n_t_17x; db_cont1.j = n_t_7x; db_cont1.k = 'b'0; db_cont1.ck = n_t_15x; db_cont1_l = !db_cont1; db_cont2.ar = !clr_all_l; db_cont2.j = n1_db2; db_cont2.k = n1_db3; db_cont2.ck = db_clk; db_cont2_l = !db_cont2; /* e13: sn7402 */ n_t_14x = !(ld_rd_buffer # n_t_13x); n1_db2 = !(n_t_20x # db_cont1_l); n1_db3 = !(db_cont3 # db_cont2_l); n1_db4 = !(db_cont3_l # db_cont4); /* e14: sn7476 */ db_cont3.ar = !clr_all_l; db_cont3.j = n1_db3; db_cont3.k = n1_db4; db_cont3.ck = db_clk; db_cont3.ap = !n3v; db_cont3_l = !db_cont3; db_cont4.ar = !db4_ena; db_cont4.j = n1_db4; db_cont4.k = n0_db4; db_cont4.ck = db_clk; db_cont4.ap = !n_t_34x; n_t_1x = !db_cont4; /* e15: ds8640n */ bmd6 = !md6_l; bmd4 = !(md_rd_buff_l # md4_l); bmd5 = !(md5_l # md_rd_buff_l); bmd7 = !md7_l; /* e16: sn7404 */ rk_data6_l = !rk_data6; rk_data1_l = !rk_data1; rk_data0_l = !rk_data0; rk_data3_l = !rk_data3; rk_data2_l = !rk_data2; rk_data5_l = !rk_data5; /* e17: sn7495 */ rk_data4.ck = !(wrt_buff_shft_l & !db_cont4_l # ld_db4 & db_cont4_l); rk_data4.d = n_t_60x & db_cont4_l # rk_data3 & !db_cont4_l; rk_data5.ck = !(wrt_buff_shft_l & !db_cont4_l # ld_db4 & db_cont4_l); rk_data5.d = n_t_40x & db_cont4_l # rk_data4 & !db_cont4_l; rk_data6.ck = !(wrt_buff_shft_l & !db_cont4_l # ld_db4 & db_cont4_l); rk_data6.d = n_t_36x & db_cont4_l # rk_data5 & !db_cont4_l; rk_data7.ck = !(wrt_buff_shft_l & !db_cont4_l # ld_db4 & db_cont4_l); rk_data7.d = n_t_39x & db_cont4_l # rk_data6 & !db_cont4_l; /* e18: sn74174 */ n_t_36x.ar = !n3v; n_t_36x.ck = db_cont3; n_t_36x.d = n_t_51x; n_t_39x.ar = !n3v; n_t_39x.ck = db_cont3; n_t_39x.d = n_t_52x; n_t_44x.ar = !n3v; n_t_44x.ck = db_cont3; n_t_44x.d = n_t_53x; n_t_57x.ar = !n3v; n_t_57x.ck = db_cont3; n_t_57x.d = n_t_54x; n_t_58x.ar = !n3v; n_t_58x.ck = db_cont3; n_t_58x.d = n_t_55x; n_t_59x.ar = !n3v; n_t_59x.ck = db_cont3; n_t_59x.d = n_t_56x; /* e19: sn7402 */ n6rk7_ok = !(n6rk7_l # btp3_l); n6rk3_ok = !(n6rk3_l # idle_l); n_t_17x = !(clr_all # n_t_16x); ld_rd_buffer = !(md_rd_buff_l # btp3_l); /* e20: sn74h00 */ wrt_buff_shft = !(lo_main_shft_l & shft_wrt_buff_l); md_rd_buff_l = !(data_enable & brk_dir_l); n_t_34x = !(main_pl & bdata1); btp3_ok_l = !(idle & btp3); /* e21: sn74h04 */ n6rk6 = !n6rk6_l; btp3_l = !btp3; btp3_ok = !btp3_ok_l; ld_db_ac = !ld_db_ac_l; n6rk3_ok_l = !n6rk3_ok; wrt_buf_data = !wt_buff_data_l; /* e22: dec8235 */ /* data4_l = !(!rk_data4_l & !enab_rk_data_l # dsk_file_rdy_l & !n6rk5_l); */ /* data5_l = !(!rk_data5_l & !enab_rk_data_l # busy_error & !n6rk5_l); */ /* data6_l = !(!rk_data6_l & !enab_rk_data_l # time_out_er & !n6rk5_l); */ /* data7_l = !(!rk_data7_l & !enab_rk_data_l # wrt_lock_er & !n6rk5_l); */ /* e23: sn7404 */ rk_data8_l = !rk_data8; rk_data10_l = !rk_data10; rk_data9_l = !rk_data9; rk_data4_l = !rk_data4; rk_data7_l = !rk_data7; rk_data11_l = !rk_data11; /* e24: sn7495 */ rk_data8.ck = !(wrt_buff_shft_l & !db_cont4_l # ld_db4 & db_cont4_l); rk_data8.d = n_t_44x & db_cont4_l # rk_data7 & !db_cont4_l; rk_data9.ck = !(wrt_buff_shft_l & !db_cont4_l # ld_db4 & db_cont4_l); rk_data9.d = n_t_57x & db_cont4_l # rk_data8 & !db_cont4_l; rk_data10.ck = !(wrt_buff_shft_l & !db_cont4_l # ld_db4 & db_cont4_l); rk_data10.d = n_t_58x & db_cont4_l # rk_data9 & !db_cont4_l; rk_data11.ck = !(wrt_buff_shft_l & !db_cont4_l # ld_db4 & db_cont4_l); rk_data11.d = n_t_59x & db_cont4_l # rk_data10 & !db_cont4_l; /* e25: sn74174 */ n_t_51x.ar = !n3v; n_t_51x.ck = db_cont2; n_t_51x.d = n_t_37x; n_t_52x.ar = !n3v; n_t_52x.ck = db_cont2; n_t_52x.d = n_t_38x; n_t_53x.ar = !n3v; n_t_53x.ck = db_cont2; n_t_53x.d = n_t_32x; n_t_54x.ar = !n3v; n_t_54x.ck = db_cont2; n_t_54x.d = n_t_31x; n_t_55x.ar = !n3v; n_t_55x.ck = db_cont2; n_t_55x.d = n_t_30x; n_t_56x.ar = !n3v; n_t_56x.ck = db_cont2; n_t_56x.d = n_t_64x; /* e26: sn74h53 */ /* gdollar_2 = !(ld_db_ac & btp3_ok # data_state & write & n12th_bit_ok # clr_all); */ /* gdollar_3 = !gdollar_2; */ db4_ena = gdollar_2; /* e27: sn7404 */ n_t_93x = !idle; md_rd_buff = !md_rd_buff_l; n_t_15x = !n_t_14x; n_t_100x = !ld_disk_addrs; hi_rd_clk_l = !hi_rd_clk; n_t_101x = !btp3; /* e28: sn7402 */ n_t_42x = !(wrt_brk_l # db_cont2_l); n_t_68x = !(n_t_42x # n_t_43x); n_t_43x = !(db_cont3 # rd_brk_l); n_t_72x = !(n_t_68x # mak_l); /* e29: dec8235 */ /* c1_l = !(!n6rk5_l # enab_rk_data); */ /* c0_l = !(!n_t_35x # n_t_3x); */ /* e30: sp384n */ btp3 = tp3; btp2 = tp2; n_t_88x = busy_error # crc_error; btp1 = tp1; /* e31: sn7404 */ n6rk7 = !n6rk7_l; device_rk_l = !device_rk; enab_rk_data_l = !enab_rk_data; wrt_buff_shft_l = !wrt_buff_shft; n6rk1 = !n6rk1_l; n6rk2 = !n6rk2_l; /* e32: sn7495 */ n_t_32x.ck = !(hi_wrt_clk & !md_rd_buff # ld_rd_buffer & md_rd_buff); n_t_32x.d = bmd8 & md_rd_buff # n_t_38x & !md_rd_buff; n_t_31x.ck = !(hi_wrt_clk & !md_rd_buff # ld_rd_buffer & md_rd_buff); n_t_31x.d = bmd9 & md_rd_buff # n_t_32x & !md_rd_buff; n_t_30x.ck = !(hi_wrt_clk & !md_rd_buff # ld_rd_buffer & md_rd_buff); n_t_30x.d = bmd10 & md_rd_buff # n_t_31x & !md_rd_buff; n_t_64x.ck = !(hi_wrt_clk & !md_rd_buff # ld_rd_buffer & md_rd_buff); n_t_64x.d = bmd11 & md_rd_buff # n_t_30x & !md_rd_buff; /* e33: sn7437 */ n3v = 'b'1; clr_all_l = !clr_all; clr_all = !(n_t_78x & n_t_73x); enab_rk_data = !(wt_buff_data_l & ld_db_ac_l); /* e34: sn7402 */ b_io_pause_l = !b_io_pause; n_t_85x = !(clr_all # ld_cmd_reg); n0_db4 = !(test_clk # clr_syn_l); n_t_70x = !(clr_all # n_t_72x); /* e35: ds8640n */ n_t_77x = !power_ok; n_t_78x = !(n_t_77x # initialize); b_io_pause = !(ts3_l # io_pause_l); n_t_71x = !data7_l; /* e36: n8881n */ /* skip_l = !(n_t_41x & n6rk1); */ /* int_rqst_l = !(n_t_41x & enab_int); */ /* internal_io_l = !device_rk; */ /* e37: dec8251 */ !n6rk1_l = !device_rk_l & !bmd9 & !bmd10 & bmd11; !n6rk2_l = !device_rk_l & !bmd9 & bmd10 & !bmd11; !n6rk3_l = !device_rk_l & !bmd9 & bmd10 & bmd11; !n6rk4_l = !device_rk_l & bmd9 & !bmd10 & !bmd11; !n6rk5_l = !device_rk_l & bmd9 & !bmd10 & bmd11; !n6rk6_l = !device_rk_l & bmd9 & bmd10 & !bmd11; !n6rk7_l = !device_rk_l & bmd9 & bmd10 & bmd11; /* e38: sn74h74 */ ac7.ar = !main; ac7.d = n_t_71x; ac7.ck = btp2; ac7.ap = !n3v; ac7_l = !ac7; b_brk_rq.ar = !n_t_70x; b_brk_rq.d = brk_rq; b_brk_rq.ck = btp1; b_brk_rq.ap = !n3v; /* e39: sn7474 */ data_rqst_late.ar = !clr_status_l; data_rqst_late.d = db_cont4_l; data_rqst_late.ck = data_clk_ok; data_rqst_late.ap = !n_t_99x; data_rqst_late_l = !data_rqst_late; done_flag_l.ar = !n_t_98x; done_flag_l.d = 'b'0; done_flag_l.ck = n_t_97x; done_flag_l.ap = !clr_status_l; done_flag = !done_flag_l; /* e40: sn7408 */ b_drive_status_er = (main_l & drive_status_er); n_t_81x = (idle & n_t_82x); n_t_35x = (n6rk3_l & ld_db_ac_l); short_tp3 = (btp3 & n_t_102x); /* e41: sn7440 */ n_t_73x = !(btp3 & bdata10_l & n6rk2 & bdata11); n_t_80x = !(n6rk3_l & n6rk6_l & n6rk4_l & n_t_79x); /* e42: ds8640n */ bmd10 = !(md10_l # md_rk_l); bmd8 = !md8_l; bmd9 = !(md9_l # md_rk_l); bmd11 = !(md_rk_l # md11_l); /* e43: sn74193 */ gdollar_4.ap = !n3v & ; gdollar_4.ar = idle # !n3v & !; gdollar_4.t = 'b'1; gdollar_4.ck = !(!n3v # !drv_revo); gdollar_5.ap = !n3v & ; gdollar_5.ar = idle # !n3v & !; gdollar_5.t = 'b'1; gdollar_5.ck = !(!n3v & !gdollar_4 # !drv_revo & gdollar_4); gdollar_6.ap = !n3v & ; gdollar_6.ar = idle # !n3v & !; gdollar_6.t = 'b'1; gdollar_6.ck = !(!n3v & !gdollar_4 & !gdollar_5 # !drv_revo & gdollar_4 & gdollar_5); set_time_out_er.ap = !n3v & ; set_time_out_er.ar = idle # !n3v & !; set_time_out_er.t = 'b'1; set_time_out_er.ck = !(!n3v & !gdollar_6 & !gdollar_4 & !gdollar_5 # !drv_revo & gdollar_6 & gdollar_4 & gdollar_5); /* e44: sn7440 */ clr_drive_cmd_l = !(bdata10 & bdata11_l & n6rk2 & btp3_ok); n_t_3x = !(n6rk6_l & n6rk5_l & n6rk2_l & n6rk4_l); /* e45: sn7400 */ n_t_79x = !(n6rk2 & bdata11_l); n_t_5x = !(enable_status & drive_status_bad); n_t_84x = !(btp3_ok & n6rk2); set_status_er = !(dsk_capacity_ex_l & n_t_6x); /* e46: sn7400 */ set_idle_pl_l = !(n_t_10x & n_t_81x); n_t_99x = !(hi_rd_clk & db_cont1); n_t_98x = !(main & last_word_pl); n_t_97x = !(n_t_95x & set_idle_pl_l); /* e47: sn7410 */ n_t_7x = !(main_l & md_rd_buff_l & data_state_l); n_t_95x = !(rdy_s_r_w_slo & enab_seek_done & idle); n_t_89x = !(data_rqst_late_l & n_t_87x & n_t_86x); /* e48: sn7408 */ n_t_90x = (n_t_88x & idle); clr_status_l = (n_t_85x & n_t_84x); n_t_83x = (short_tp3 & idle_l); set_busy_er = (n_t_80x & n_t_83x); /* e49: dec8235 */ /* data8_l = !(!rk_data8_l & !enab_rk_data_l # crc_error & !n6rk5_l); */ /* data9_l = !(!rk_data9_l & !enab_rk_data_l # data_rqst_late & !n6rk5_l); */ /* data10_l = !(!rk_data10_l & !enab_rk_data_l # drive_status_er & !n6rk5_l); */ /* data11_l = !(!rk_data11_l & !enab_rk_data_l # cyl_addrs_er & !n6rk5_l); */ /* e50: sn7496 */ busy_error.ck = n3v; busy_error.d = 'b'1; busy_error.ap = n3v & set_busy_er; busy_error.ar = !n3v & !clr_status_l; crc_error.ck = n3v; crc_error.d = busy_error; crc_error.ap = n3v & set_crc_er; crc_error.ar = !n3v & !clr_status_l; time_out_er.ck = n3v; time_out_er.d = crc_error; time_out_er.ap = n3v & set_time_out_er; time_out_er.ar = !n3v & !clr_status_l; drive_status_er.ck = n3v; drive_status_er.d = time_out_er; drive_status_er.ap = n3v & set_status_er; drive_status_er.ar = !n3v & !clr_status_l; cyl_addrs_er.ck = n3v; cyl_addrs_er.d = drive_status_er; cyl_addrs_er.ap = n3v & set_cyl_addrs_er; cyl_addrs_er.ar = !n3v & !clr_status_l; /* e51: sn7402 */ md_rk_l = !(md_rd_buff # b_io_pause); set_crc_er = !(not_equal_l # end_state_l); set_cyl_addrs_er = !(not_equal_l # sector_seek_l); n_t_12x = !(wrt_cmd_l # dsk_wrt_status_l); /* e52: sn7474 */ wrt_lock_er.ar = !clr_status_l; wrt_lock_er.d = n_t_12x; wrt_lock_er.ck = ld_disk_addrs; wrt_lock_er.ap = !n3v; wrt_lock_er_l = !wrt_lock_er; clr_syn_l.ar = !n3v; clr_syn_l.d = 'b'0; clr_syn_l.ck = n_t_19x; clr_syn_l.ap = !db_cont4; /* e53: sn7402 */ n_t_87x = !(cyl_addrs_er # b_drive_status_er); n_t_86x = !(wrt_lock_er # time_out_er); error_fl_l = !(n_t_89x # n_t_88x); error_clr_l = !(n_t_89x # n_t_90x); /* e54: sn7400 */ n_t_41x = !(error_fl_l & done_flag_l); enable_status = !(clr_drive_cmd_l & n_t_100x); n_t_19x = !(btp2 & wrt_buf_data); ld_db_ac_l = !(ac7 & n6rk7); /* Open collector 'wire-or's */ property atmel {open_collector= c0_l}; !c0_l = (!n_t_35x # n_t_3x); c0_l.oe = (!n_t_35x # n_t_3x); property atmel {open_collector= c1_l}; !c1_l = (!n6rk5_l # enab_rk_data); c1_l.oe = (!n6rk5_l # enab_rk_data); property atmel {open_collector= data0_l}; !data0_l = (!rk_data0_l & !enab_rk_data_l # done_flag & !n6rk5_l); data0_l.oe = (!rk_data0_l & !enab_rk_data_l # done_flag & !n6rk5_l); property atmel {open_collector= data10_l}; !data10_l = (!rk_data10_l & !enab_rk_data_l # drive_status_er & !n6rk5_l); data10_l.oe = (!rk_data10_l & !enab_rk_data_l # drive_status_er & !n6rk5_l); property atmel {open_collector= data11_l}; !data11_l = (!rk_data11_l & !enab_rk_data_l # cyl_addrs_er & !n6rk5_l); data11_l.oe = (!rk_data11_l & !enab_rk_data_l # cyl_addrs_er & !n6rk5_l); property atmel {open_collector= data1_l}; !data1_l = (!rk_data1_l & !enab_rk_data_l # rdy_s_r_w_l & !n6rk5_l); data1_l.oe = (!rk_data1_l & !enab_rk_data_l # rdy_s_r_w_l & !n6rk5_l); property atmel {open_collector= data2_l}; !data2_l = (!rk_data2_l & !enab_rk_data_l); data2_l.oe = (!rk_data2_l & !enab_rk_data_l); property atmel {open_collector= data3_l}; !data3_l = (!rk_data3_l & !enab_rk_data_l # seek_fail & !n6rk5_l); data3_l.oe = (!rk_data3_l & !enab_rk_data_l # seek_fail & !n6rk5_l); property atmel {open_collector= data4_l}; !data4_l = (!rk_data4_l & !enab_rk_data_l # dsk_file_rdy_l & !n6rk5_l); data4_l.oe = (!rk_data4_l & !enab_rk_data_l # dsk_file_rdy_l & !n6rk5_l); property atmel {open_collector= data5_l}; !data5_l = (!rk_data5_l & !enab_rk_data_l # busy_error & !n6rk5_l); data5_l.oe = (!rk_data5_l & !enab_rk_data_l # busy_error & !n6rk5_l); property atmel {open_collector= data6_l}; !data6_l = (!rk_data6_l & !enab_rk_data_l # time_out_er & !n6rk5_l); data6_l.oe = (!rk_data6_l & !enab_rk_data_l # time_out_er & !n6rk5_l); property atmel {open_collector= data7_l}; !data7_l = (!rk_data7_l & !enab_rk_data_l # wrt_lock_er & !n6rk5_l); data7_l.oe = (!rk_data7_l & !enab_rk_data_l # wrt_lock_er & !n6rk5_l); property atmel {open_collector= data8_l}; !data8_l = (!rk_data8_l & !enab_rk_data_l # crc_error & !n6rk5_l); data8_l.oe = (!rk_data8_l & !enab_rk_data_l # crc_error & !n6rk5_l); property atmel {open_collector= data9_l}; !data9_l = (!rk_data9_l & !enab_rk_data_l # data_rqst_late & !n6rk5_l); data9_l.oe = (!rk_data9_l & !enab_rk_data_l # data_rqst_late & !n6rk5_l); !gdollar_0 = (n1_db2 # db4_ena & n1_db4 # n0_db4 # n1_db3); !gdollar_1 = gdollar_0; !gdollar_2 = (ld_db_ac & btp3_ok # data_state & write & n12th_bit_ok # clr_all); !gdollar_3 = gdollar_2; property atmel {open_collector= int_rqst_l}; !int_rqst_l = (n_t_41x & enab_int); int_rqst_l.oe = (n_t_41x & enab_int); property atmel {open_collector= internal_io_l}; !internal_io_l = device_rk; internal_io_l.oe = device_rk; property atmel {open_collector= skip_l}; !skip_l = (n_t_41x & n6rk1); skip_l.oe = (n_t_41x & n6rk1);