// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: c_us 
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// c11: c_us 
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// c52: c_us 
// c53: cpol_use 
// c54: cpol_use 
// c55: cpol_use 
// c56: c_us 
// e1: sp314n 
module m7104b (bdata1, bdata10, bdata10_l, bdata11, bdata11_l, brk_dir_l, brk_rq, data_clk_ok, data_enable, data_state, data_state_l, db_cont4_l, drive_status_bad, drv_revo, dsk_capacity_ex_l, dsk_file_rdy_l, dsk_wrt_status_l, enab_int, enab_seek_done, end_state_l, hi_data_in, hi_rd_clk, idle, idle_l, last_word_pl, ld_cmd_reg, ld_disk_addrs, lo_main_data, lo_main_shft_l, main, main_l, main_pl, mak_l, n12th_bit_ok, n_t_102x, n_t_10x, n_t_20x, n_t_24x, n_t_25x, n_t_27x, n_t_6x, n_t_74x, n_t_75x, n_t_76x, n_t_8x, not_equal_l, rd_brk_l, rdy_s_r_w_l, rdy_s_r_w_slo, sector_seek_l, seek_fail, shft_wrt_buff_l, write, wrt_brk_l, wrt_cmd_l, wt_buff_data_l, ac7_l, b_brk_rq, bmd6, bmd7, bmd8, btp2, btp3, btp3_l, btp3_ok, busy_error, c0_l, c1_l, clr_all, clr_all_l, clr_drive_cmd_l, crc_error, data0_l, data10_l, data11_l, data1_l, data2_l, data3_l, data4_l, data5_l, data6_l, data7_l, data8_l, data9_l, db_clk, db_cont1_l, db_cont2, db_cont4, device_rk, error_clr_l, initialize, int_rqst_l, internal_io_l, io_pause_l, md0_l, md10_l, md11_l, md1_l, md2_l, md3_l, md4_l, md5_l, md6_l, md7_l, md8_l, md9_l, md_rd_buff_l, md_rk_l, n3v, n6rk2_l, n6rk3_ok, n6rk3_ok_l, n6rk4_l, n6rk6, n6rk7, n6rk7_ok, n_t_101x, n_t_1x, n_t_22x, n_t_5x, n_t_82x, n_t_93x, power_ok, rk_data11, set_idle_pl_l, skip_l, test_clk, test_clk_l, tp1, tp2, tp3, ts3_l);
input bdata1;
input bdata10;
input bdata10_l;
input bdata11;
input bdata11_l;
input brk_dir_l;
input brk_rq;
input data_clk_ok;
input data_enable;
input data_state;
input data_state_l;
input db_cont4_l;
input drive_status_bad;
input drv_revo;
input dsk_capacity_ex_l;
input dsk_file_rdy_l;
input dsk_wrt_status_l;
input enab_int;
input enab_seek_done;
input end_state_l;
input hi_data_in;
input hi_rd_clk;
input idle;
input idle_l;
input last_word_pl;
input ld_cmd_reg;
input ld_disk_addrs;
input lo_main_data;
input lo_main_shft_l;
input main;
input main_l;
input main_pl;
input mak_l;
input n12th_bit_ok;
input n_t_102x;
input n_t_10x;
input n_t_20x;
output n_t_24x;
output n_t_25x;
output n_t_27x;
input n_t_6x;
input n_t_74x;
input n_t_75x;
input n_t_76x;
output n_t_8x;
input not_equal_l;
input rd_brk_l;
input rdy_s_r_w_l;
input rdy_s_r_w_slo;
input sector_seek_l;
input seek_fail;
input shft_wrt_buff_l;
input write;
input wrt_brk_l;
input wrt_cmd_l;
input wt_buff_data_l;
output ac7_l;
output reg b_brk_rq;
inout bmd6;
inout bmd7;
inout bmd8;
inout btp2;
inout btp3;
inout btp3_l;
inout btp3_ok;
inout reg busy_error;
output c0_l;
output c1_l;
inout clr_all;
inout clr_all_l;
inout clr_drive_cmd_l;
inout reg crc_error;
output data0_l;
output data10_l;
output data11_l;
output data1_l;
output data2_l;
output data3_l;
output data4_l;
output data5_l;
output data6_l;
inout data7_l;
output data8_l;
output data9_l;
input db_clk;
inout db_cont1_l;
inout reg db_cont2;
inout reg db_cont4;
inout device_rk;
output error_clr_l;
input initialize;
output int_rqst_l;
output internal_io_l;
input io_pause_l;
input md0_l;
input md10_l;
input md11_l;
input md1_l;
input md2_l;
input md3_l;
input md4_l;
input md5_l;
input md6_l;
input md7_l;
input md8_l;
input md9_l;
inout md_rd_buff_l;
inout md_rk_l;
inout n3v;
inout n6rk2_l;
inout n6rk3_ok;
output n6rk3_ok_l;
inout n6rk4_l;
output n6rk6;
inout n6rk7;
output n6rk7_ok;
output n_t_101x;
output n_t_1x;
output n_t_22x;
output n_t_5x;
input n_t_82x;
output n_t_93x;
input power_ok;
inout reg rk_data11;
inout set_idle_pl_l;
output skip_l;
input test_clk;
output test_clk_l;
input tp1;
input tp2;
input tp3;
input ts3_l;

reg ac7_m;
reg b_brk_rq_m;
reg busy_error_m;
reg clr_syn_l_m;
reg crc_error_m;
reg cyl_addrs_er_m;
reg data_rqst_late_m;
reg db_cont1_m;
reg db_cont2_m;
reg db_cont3_m;
reg db_cont4_m;
reg done_flag_l_m;
reg drive_status_er_m;
reg gdollar_4_m;
reg gdollar_5_m;
reg gdollar_6_m;
reg n_t_36x_m;
reg n_t_39x_m;
reg n_t_40x_m;
reg n_t_44x_m;
reg n_t_45x_m;
reg n_t_46x_m;
reg n_t_47x_m;
reg n_t_48x_m;
reg n_t_49x_m;
reg n_t_50x_m;
reg n_t_51x_m;
reg n_t_52x_m;
reg n_t_53x_m;
reg n_t_54x_m;
reg n_t_55x_m;
reg n_t_56x_m;
reg n_t_57x_m;
reg n_t_58x_m;
reg n_t_59x_m;
reg n_t_60x_m;
reg n_t_61x_m;
reg n_t_65x_m;
reg n_t_66x_m;
reg n_t_67x_m;
reg set_time_out_er_m;
reg time_out_er_m;
reg wrt_lock_er_m;

reg n_t_18x;
reg n_t_23x;
reg n_t_26x;
reg n_t_28x;
reg n_t_45x;
reg n_t_46x;
reg n_t_47x;
reg n_t_48x;
reg n_t_49x;
reg n_t_50x;
reg n_t_63x;
reg n_t_62x;
reg n_t_37x;
reg n_t_38x;
reg rk_data0;
reg rk_data1;
reg rk_data2;
reg rk_data3;
reg n_t_67x;
reg n_t_66x;
reg n_t_65x;
reg n_t_61x;
reg n_t_60x;
reg n_t_40x;
reg db_cont1;
reg db_cont3;
reg rk_data4;
reg rk_data5;
reg rk_data6;
reg rk_data7;
reg n_t_36x;
reg n_t_39x;
reg n_t_44x;
reg n_t_57x;
reg n_t_58x;
reg n_t_59x;
reg rk_data8;
reg rk_data9;
reg rk_data10;
reg n_t_51x;
reg n_t_52x;
reg n_t_53x;
reg n_t_54x;
reg n_t_55x;
reg n_t_56x;
reg n_t_32x;
reg n_t_31x;
reg n_t_30x;
reg n_t_64x;
reg ac7;
reg data_rqst_late;
reg done_flag_l;
reg gdollar_4;
reg gdollar_5;
reg gdollar_6;
reg set_time_out_er;
reg time_out_er;
reg drive_status_er;
reg cyl_addrs_er;
reg wrt_lock_er;
reg clr_syn_l;
wire b_drive_status_er;
wire b_io_pause;
wire bmd0;
wire bmd1;
wire bmd10;
wire bmd11;
wire bmd2;
wire bmd3;
wire bmd4;
wire bmd5;
wire bmd9;
wire btp3_ok_l;
wire clr_status_l;
wire db4_ena;
wire enab_rk_data;
wire enable_status;
wire error_fl_l;
wire hi_wrt_clk;
wire ld_db4;
wire ld_db_ac_l;
wire ld_rd_buffer;
wire n0_db4;
wire n1_db2;
wire n1_db3;
wire n1_db4;
wire n6rk1_l;
wire n6rk3_l;
wire n6rk5_l;
wire n6rk6_l;
wire n6rk7_l;
wire n_t_12x;
wire n_t_13x;
wire n_t_14x;
wire n_t_16x;
wire n_t_17x;
wire n_t_19x;
wire n_t_34x;
wire n_t_35x;
wire n_t_3x;
wire n_t_41x;
wire n_t_42x;
wire n_t_43x;
wire n_t_68x;
wire n_t_70x;
wire n_t_72x;
wire n_t_73x;
wire n_t_78x;
wire n_t_79x;
wire n_t_7x;
wire n_t_80x;
wire n_t_81x;
wire n_t_83x;
wire n_t_84x;
wire n_t_85x;
wire n_t_86x;
wire n_t_87x;
wire n_t_88x;
wire n_t_89x;
wire n_t_90x;
wire n_t_95x;
wire n_t_97x;
wire n_t_98x;
wire n_t_99x;
wire set_busy_er;
wire set_crc_er;
wire set_cyl_addrs_er;
wire set_status_er;
wire short_tp3;
wire wrt_buff_shft;
assign device_rk = ~(n_t_74x
                      | n_t_75x
                      | n_t_76x
                      | md5_l
                      | md4_l
                      | ~b_io_pause
                      | md3_l);
// e2: ds8640n 
assign bmd2 = ~(md2_l
                 | md_rd_buff_l);
assign bmd0 = ~(md_rd_buff_l
                 | md0_l);
assign bmd1 = ~(md1_l
                 | md_rd_buff_l);
assign bmd3 = ~(md_rd_buff_l
                 | md3_l);
// e3: sn7495 
always @(negedge (hi_wrt_clk & md_rd_buff_l
                       | ld_rd_buffer & ~md_rd_buff_l))
  if (~(hi_wrt_clk & md_rd_buff_l
                       | ld_rd_buffer & ~md_rd_buff_l)) begin
    n_t_18x <= bmd0 & ~md_rd_buff_l
                    | hi_data_in & md_rd_buff_l;
  end
always @(negedge (hi_wrt_clk & md_rd_buff_l
                       | ld_rd_buffer & ~md_rd_buff_l))
  if (~(hi_wrt_clk & md_rd_buff_l
                       | ld_rd_buffer & ~md_rd_buff_l)) begin
    n_t_23x <= bmd1 & ~md_rd_buff_l
                    | n_t_18x & md_rd_buff_l;
  end
always @(negedge (hi_wrt_clk & md_rd_buff_l
                       | ld_rd_buffer & ~md_rd_buff_l))
  if (~(hi_wrt_clk & md_rd_buff_l
                       | ld_rd_buffer & ~md_rd_buff_l)) begin
    n_t_26x <= bmd2 & ~md_rd_buff_l
                    | n_t_23x & md_rd_buff_l;
  end
always @(negedge (hi_wrt_clk & md_rd_buff_l
                       | ld_rd_buffer & ~md_rd_buff_l))
  if (~(hi_wrt_clk & md_rd_buff_l
                       | ld_rd_buffer & ~md_rd_buff_l)) begin
    n_t_28x <= bmd3 & ~md_rd_buff_l
                    | n_t_26x & md_rd_buff_l;
  end
// e4: sn74174 
always @(db_cont2, n3v, n_t_18x)
  if (~n3v) begin
    n_t_45x_m <= 1'b0;
  end else
  if (~(db_cont2)) begin
    n_t_45x_m <= n_t_18x;
  end
always @(db_cont2, n3v, n_t_45x_m)
  if (~n3v) begin
    n_t_45x <= 1'b0;
  end else
  if (db_cont2) begin
    n_t_45x <= n_t_45x_m;
  end
always @(db_cont2, n3v, n_t_23x)
  if (~n3v) begin
    n_t_46x_m <= 1'b0;
  end else
  if (~(db_cont2)) begin
    n_t_46x_m <= n_t_23x;
  end
always @(db_cont2, n3v, n_t_46x_m)
  if (~n3v) begin
    n_t_46x <= 1'b0;
  end else
  if (db_cont2) begin
    n_t_46x <= n_t_46x_m;
  end
always @(db_cont2, n3v, n_t_26x)
  if (~n3v) begin
    n_t_47x_m <= 1'b0;
  end else
  if (~(db_cont2)) begin
    n_t_47x_m <= n_t_26x;
  end
always @(db_cont2, n3v, n_t_47x_m)
  if (~n3v) begin
    n_t_47x <= 1'b0;
  end else
  if (db_cont2) begin
    n_t_47x <= n_t_47x_m;
  end
always @(db_cont2, n3v, n_t_28x)
  if (~n3v) begin
    n_t_48x_m <= 1'b0;
  end else
  if (~(db_cont2)) begin
    n_t_48x_m <= n_t_28x;
  end
always @(db_cont2, n3v, n_t_48x_m)
  if (~n3v) begin
    n_t_48x <= 1'b0;
  end else
  if (db_cont2) begin
    n_t_48x <= n_t_48x_m;
  end
always @(db_cont2, n3v, n_t_63x)
  if (~n3v) begin
    n_t_49x_m <= 1'b0;
  end else
  if (~(db_cont2)) begin
    n_t_49x_m <= n_t_63x;
  end
always @(db_cont2, n3v, n_t_49x_m)
  if (~n3v) begin
    n_t_49x <= 1'b0;
  end else
  if (db_cont2) begin
    n_t_49x <= n_t_49x_m;
  end
always @(db_cont2, n3v, n_t_62x)
  if (~n3v) begin
    n_t_50x_m <= 1'b0;
  end else
  if (~(db_cont2)) begin
    n_t_50x_m <= n_t_62x;
  end
always @(db_cont2, n3v, n_t_50x_m)
  if (~n3v) begin
    n_t_50x <= 1'b0;
  end else
  if (db_cont2) begin
    n_t_50x <= n_t_50x_m;
  end
// e5: sn7495 
always @(negedge (hi_wrt_clk & md_rd_buff_l
                       | ld_rd_buffer & ~md_rd_buff_l))
  if (~(hi_wrt_clk & md_rd_buff_l
                       | ld_rd_buffer & ~md_rd_buff_l)) begin
    n_t_63x <= bmd4 & ~md_rd_buff_l
                    | n_t_28x & md_rd_buff_l;
  end
always @(negedge (hi_wrt_clk & md_rd_buff_l
                       | ld_rd_buffer & ~md_rd_buff_l))
  if (~(hi_wrt_clk & md_rd_buff_l
                       | ld_rd_buffer & ~md_rd_buff_l)) begin
    n_t_62x <= bmd5 & ~md_rd_buff_l
                    | n_t_63x & md_rd_buff_l;
  end
always @(negedge (hi_wrt_clk & md_rd_buff_l
                       | ld_rd_buffer & ~md_rd_buff_l))
  if (~(hi_wrt_clk & md_rd_buff_l
                       | ld_rd_buffer & ~md_rd_buff_l)) begin
    n_t_37x <= bmd6 & ~md_rd_buff_l
                    | n_t_62x & md_rd_buff_l;
  end
always @(negedge (hi_wrt_clk & md_rd_buff_l
                       | ld_rd_buffer & ~md_rd_buff_l))
  if (~(hi_wrt_clk & md_rd_buff_l
                       | ld_rd_buffer & ~md_rd_buff_l)) begin
    n_t_38x <= bmd7 & ~md_rd_buff_l
                    | n_t_37x & md_rd_buff_l;
  end
// e6: sn74h53 
// gdollar_0 = !(n1_db2
//          # db4_ena & n1_db4
//          # n0_db4
//          # n1_db3); 
// !gdollar_0 = !gdollar_0; 
assign n_t_22x = gdollar_0;
// e8: dec8235 
// data0_l = !(rk_data0 & enab_rk_data
//        # !done_flag_l & !n6rk5_l); 
// data1_l = !(rk_data1 & enab_rk_data
//        # rdy_s_r_w_l & !n6rk5_l); 
// data2_l = !(rk_data2 & enab_rk_data); 
// data3_l = !(rk_data3 & enab_rk_data
//        # seek_fail & !n6rk5_l); 
// e9: sn7495 
always @(negedge (~wrt_buff_shft & ~db_cont4_l
                        | ld_db4 & db_cont4_l))
  if (~(~wrt_buff_shft & ~db_cont4_l
                        | ld_db4 & db_cont4_l)) begin
    rk_data0 <= n_t_67x & db_cont4_l
                     | lo_main_data & ~db_cont4_l;
  end
always @(negedge (~wrt_buff_shft & ~db_cont4_l
                        | ld_db4 & db_cont4_l))
  if (~(~wrt_buff_shft & ~db_cont4_l
                        | ld_db4 & db_cont4_l)) begin
    rk_data1 <= n_t_66x & db_cont4_l
                     | rk_data0 & ~db_cont4_l;
  end
always @(negedge (~wrt_buff_shft & ~db_cont4_l
                        | ld_db4 & db_cont4_l))
  if (~(~wrt_buff_shft & ~db_cont4_l
                        | ld_db4 & db_cont4_l)) begin
    rk_data2 <= n_t_65x & db_cont4_l
                     | rk_data1 & ~db_cont4_l;
  end
always @(negedge (~wrt_buff_shft & ~db_cont4_l
                        | ld_db4 & db_cont4_l))
  if (~(~wrt_buff_shft & ~db_cont4_l
                        | ld_db4 & db_cont4_l)) begin
    rk_data3 <= n_t_61x & db_cont4_l
                     | rk_data2 & ~db_cont4_l;
  end
// e10: sn74174 
always @(db_cont3, n3v, n_t_45x)
  if (~n3v) begin
    n_t_67x_m <= 1'b0;
  end else
  if (~(db_cont3)) begin
    n_t_67x_m <= n_t_45x;
  end
always @(db_cont3, n3v, n_t_67x_m)
  if (~n3v) begin
    n_t_67x <= 1'b0;
  end else
  if (db_cont3) begin
    n_t_67x <= n_t_67x_m;
  end
always @(db_cont3, n3v, n_t_46x)
  if (~n3v) begin
    n_t_66x_m <= 1'b0;
  end else
  if (~(db_cont3)) begin
    n_t_66x_m <= n_t_46x;
  end
always @(db_cont3, n3v, n_t_66x_m)
  if (~n3v) begin
    n_t_66x <= 1'b0;
  end else
  if (db_cont3) begin
    n_t_66x <= n_t_66x_m;
  end
always @(db_cont3, n3v, n_t_47x)
  if (~n3v) begin
    n_t_65x_m <= 1'b0;
  end else
  if (~(db_cont3)) begin
    n_t_65x_m <= n_t_47x;
  end
always @(db_cont3, n3v, n_t_65x_m)
  if (~n3v) begin
    n_t_65x <= 1'b0;
  end else
  if (db_cont3) begin
    n_t_65x <= n_t_65x_m;
  end
always @(db_cont3, n3v, n_t_48x)
  if (~n3v) begin
    n_t_61x_m <= 1'b0;
  end else
  if (~(db_cont3)) begin
    n_t_61x_m <= n_t_48x;
  end
always @(db_cont3, n3v, n_t_61x_m)
  if (~n3v) begin
    n_t_61x <= 1'b0;
  end else
  if (db_cont3) begin
    n_t_61x <= n_t_61x_m;
  end
always @(db_cont3, n3v, n_t_49x)
  if (~n3v) begin
    n_t_60x_m <= 1'b0;
  end else
  if (~(db_cont3)) begin
    n_t_60x_m <= n_t_49x;
  end
always @(db_cont3, n3v, n_t_60x_m)
  if (~n3v) begin
    n_t_60x <= 1'b0;
  end else
  if (db_cont3) begin
    n_t_60x <= n_t_60x_m;
  end
always @(db_cont3, n3v, n_t_50x)
  if (~n3v) begin
    n_t_40x_m <= 1'b0;
  end else
  if (~(db_cont3)) begin
    n_t_40x_m <= n_t_50x;
  end
always @(db_cont3, n3v, n_t_40x_m)
  if (~n3v) begin
    n_t_40x <= 1'b0;
  end else
  if (db_cont3) begin
    n_t_40x <= n_t_40x_m;
  end
// e11: sn7408 
assign n_t_13x = (n12th_bit_ok & wrt_cmd_l);
assign n_t_16x = (n1_db2 & db_cont2);
assign ld_db4 = (n1_db4 & db_clk);
assign hi_wrt_clk = (~hi_rd_clk & wrt_cmd_l);
// e12: sn7473 
always @(n_t_14x, n_t_17x, n_t_7x, db_cont1)
  if (~n_t_17x) begin
    db_cont1_m <= 1'b0;
  end else
  if (~(~n_t_14x)) begin
    db_cont1_m <= n_t_7x? (1'b0? ~db_cont1: 1'b1) : (1'b0? 1'b0: db_cont1);
  end
always @(n_t_14x, n_t_17x, db_cont1_m)
  if (~n_t_17x) begin
    db_cont1 <= 1'b0;
  end else
  if (~n_t_14x) begin
    db_cont1 <= db_cont1_m;
  end
assign db_cont1_l = ~db_cont1;
always @(db_clk, clr_all_l, n1_db2, n1_db3, db_cont2)
  if (~clr_all_l) begin
    db_cont2_m <= 1'b0;
  end else
  if (~(db_clk)) begin
    db_cont2_m <= n1_db2? (n1_db3? ~db_cont2: 1'b1) : (n1_db3? 1'b0: db_cont2);
  end
always @(db_clk, clr_all_l, db_cont2_m)
  if (~clr_all_l) begin
    db_cont2 <= 1'b0;
  end else
  if (db_clk) begin
    db_cont2 <= db_cont2_m;
  end
// e13: sn7402 
assign n_t_14x = ~(ld_rd_buffer
                    | n_t_13x);
assign n1_db2 = ~(n_t_20x
                   | db_cont1_l);
assign n1_db3 = ~(db_cont3
                   | ~db_cont2);
assign n1_db4 = ~(~db_cont3
                   | db_cont4);
// e14: sn7476 
always @(db_clk, clr_all_l, n3v, n1_db3, n1_db4, db_cont3)
  if (~clr_all_l) begin
    db_cont3_m <= 1'b0;
  end else
  if (~n3v) begin
    db_cont3_m <= 1'b1;
  end else
  if (~(db_clk)) begin
    db_cont3_m <= n1_db3? (n1_db4? ~db_cont3: 1'b1) : (n1_db4? 1'b0: db_cont3);
  end
always @(db_clk, clr_all_l, n3v, db_cont3_m)
  if (~clr_all_l) begin
    db_cont3 <= 1'b0;
  end else
  if (~n3v) begin
    db_cont3 <= 1'b1;
  end else
  if (db_clk) begin
    db_cont3 <= db_cont3_m;
  end
always @(db_clk, db4_ena, n_t_34x, n1_db4, n0_db4, db_cont4)
  if (~db4_ena) begin
    db_cont4_m <= 1'b0;
  end else
  if (~n_t_34x) begin
    db_cont4_m <= 1'b1;
  end else
  if (~(db_clk)) begin
    db_cont4_m <= n1_db4? (n0_db4? ~db_cont4: 1'b1) : (n0_db4? 1'b0: db_cont4);
  end
always @(db_clk, db4_ena, n_t_34x, db_cont4_m)
  if (~db4_ena) begin
    db_cont4 <= 1'b0;
  end else
  if (~n_t_34x) begin
    db_cont4 <= 1'b1;
  end else
  if (db_clk) begin
    db_cont4 <= db_cont4_m;
  end
assign n_t_1x = ~db_cont4;
// e15: ds8640n 
assign bmd6 = ~md6_l;
assign bmd4 = ~(md_rd_buff_l
                 | md4_l);
assign bmd5 = ~(md5_l
                 | md_rd_buff_l);
assign bmd7 = ~md7_l;
// e16: sn7404 
// e17: sn7495 
always @(negedge (~wrt_buff_shft & ~db_cont4_l
                        | ld_db4 & db_cont4_l))
  if (~(~wrt_buff_shft & ~db_cont4_l
                        | ld_db4 & db_cont4_l)) begin
    rk_data4 <= n_t_60x & db_cont4_l
                     | rk_data3 & ~db_cont4_l;
  end
always @(negedge (~wrt_buff_shft & ~db_cont4_l
                        | ld_db4 & db_cont4_l))
  if (~(~wrt_buff_shft & ~db_cont4_l
                        | ld_db4 & db_cont4_l)) begin
    rk_data5 <= n_t_40x & db_cont4_l
                     | rk_data4 & ~db_cont4_l;
  end
always @(negedge (~wrt_buff_shft & ~db_cont4_l
                        | ld_db4 & db_cont4_l))
  if (~(~wrt_buff_shft & ~db_cont4_l
                        | ld_db4 & db_cont4_l)) begin
    rk_data6 <= n_t_36x & db_cont4_l
                     | rk_data5 & ~db_cont4_l;
  end
always @(negedge (~wrt_buff_shft & ~db_cont4_l
                        | ld_db4 & db_cont4_l))
  if (~(~wrt_buff_shft & ~db_cont4_l
                        | ld_db4 & db_cont4_l)) begin
    rk_data7 <= n_t_39x & db_cont4_l
                     | rk_data6 & ~db_cont4_l;
  end
// e18: sn74174 
always @(db_cont3, n3v, n_t_51x)
  if (~n3v) begin
    n_t_36x_m <= 1'b0;
  end else
  if (~(db_cont3)) begin
    n_t_36x_m <= n_t_51x;
  end
always @(db_cont3, n3v, n_t_36x_m)
  if (~n3v) begin
    n_t_36x <= 1'b0;
  end else
  if (db_cont3) begin
    n_t_36x <= n_t_36x_m;
  end
always @(db_cont3, n3v, n_t_52x)
  if (~n3v) begin
    n_t_39x_m <= 1'b0;
  end else
  if (~(db_cont3)) begin
    n_t_39x_m <= n_t_52x;
  end
always @(db_cont3, n3v, n_t_39x_m)
  if (~n3v) begin
    n_t_39x <= 1'b0;
  end else
  if (db_cont3) begin
    n_t_39x <= n_t_39x_m;
  end
always @(db_cont3, n3v, n_t_53x)
  if (~n3v) begin
    n_t_44x_m <= 1'b0;
  end else
  if (~(db_cont3)) begin
    n_t_44x_m <= n_t_53x;
  end
always @(db_cont3, n3v, n_t_44x_m)
  if (~n3v) begin
    n_t_44x <= 1'b0;
  end else
  if (db_cont3) begin
    n_t_44x <= n_t_44x_m;
  end
always @(db_cont3, n3v, n_t_54x)
  if (~n3v) begin
    n_t_57x_m <= 1'b0;
  end else
  if (~(db_cont3)) begin
    n_t_57x_m <= n_t_54x;
  end
always @(db_cont3, n3v, n_t_57x_m)
  if (~n3v) begin
    n_t_57x <= 1'b0;
  end else
  if (db_cont3) begin
    n_t_57x <= n_t_57x_m;
  end
always @(db_cont3, n3v, n_t_55x)
  if (~n3v) begin
    n_t_58x_m <= 1'b0;
  end else
  if (~(db_cont3)) begin
    n_t_58x_m <= n_t_55x;
  end
always @(db_cont3, n3v, n_t_58x_m)
  if (~n3v) begin
    n_t_58x <= 1'b0;
  end else
  if (db_cont3) begin
    n_t_58x <= n_t_58x_m;
  end
always @(db_cont3, n3v, n_t_56x)
  if (~n3v) begin
    n_t_59x_m <= 1'b0;
  end else
  if (~(db_cont3)) begin
    n_t_59x_m <= n_t_56x;
  end
always @(db_cont3, n3v, n_t_59x_m)
  if (~n3v) begin
    n_t_59x <= 1'b0;
  end else
  if (db_cont3) begin
    n_t_59x <= n_t_59x_m;
  end
// e19: sn7402 
assign n6rk7_ok = ~(n6rk7_l
                     | btp3_l);
assign n6rk3_ok = ~(n6rk3_l
                     | idle_l);
assign n_t_17x = ~(clr_all
                    | n_t_16x);
assign ld_rd_buffer = ~(md_rd_buff_l
                         | btp3_l);
// e20: sn74h00 
assign wrt_buff_shft = ~(lo_main_shft_l & shft_wrt_buff_l);
assign md_rd_buff_l = ~(data_enable & brk_dir_l);
assign n_t_34x = ~(main_pl & bdata1);
assign btp3_ok_l = ~(idle & btp3);
// e21: sn74h04 
assign n6rk6 = ~n6rk6_l;
assign btp3_l = ~btp3;
assign btp3_ok = ~btp3_ok_l;
assign n6rk3_ok_l = ~n6rk3_ok;
// e22: dec8235 
// data4_l = !(rk_data4 & enab_rk_data
//        # dsk_file_rdy_l & !n6rk5_l); 
// data5_l = !(rk_data5 & enab_rk_data
//        # busy_error & !n6rk5_l); 
// data6_l = !(rk_data6 & enab_rk_data
//        # time_out_er & !n6rk5_l); 
// data7_l = !(rk_data7 & enab_rk_data
//        # wrt_lock_er & !n6rk5_l); 
// e23: sn7404 
// e24: sn7495 
always @(negedge (~wrt_buff_shft & ~db_cont4_l
                        | ld_db4 & db_cont4_l))
  if (~(~wrt_buff_shft & ~db_cont4_l
                        | ld_db4 & db_cont4_l)) begin
    rk_data8 <= n_t_44x & db_cont4_l
                     | rk_data7 & ~db_cont4_l;
  end
always @(negedge (~wrt_buff_shft & ~db_cont4_l
                        | ld_db4 & db_cont4_l))
  if (~(~wrt_buff_shft & ~db_cont4_l
                        | ld_db4 & db_cont4_l)) begin
    rk_data9 <= n_t_57x & db_cont4_l
                     | rk_data8 & ~db_cont4_l;
  end
always @(negedge (~wrt_buff_shft & ~db_cont4_l
                         | ld_db4 & db_cont4_l))
  if (~(~wrt_buff_shft & ~db_cont4_l
                         | ld_db4 & db_cont4_l)) begin
    rk_data10 <= n_t_58x & db_cont4_l
                      | rk_data9 & ~db_cont4_l;
  end
always @(negedge (~wrt_buff_shft & ~db_cont4_l
                         | ld_db4 & db_cont4_l))
  if (~(~wrt_buff_shft & ~db_cont4_l
                         | ld_db4 & db_cont4_l)) begin
    rk_data11 <= n_t_59x & db_cont4_l
                      | rk_data10 & ~db_cont4_l;
  end
// e25: sn74174 
always @(db_cont2, n3v, n_t_37x)
  if (~n3v) begin
    n_t_51x_m <= 1'b0;
  end else
  if (~(db_cont2)) begin
    n_t_51x_m <= n_t_37x;
  end
always @(db_cont2, n3v, n_t_51x_m)
  if (~n3v) begin
    n_t_51x <= 1'b0;
  end else
  if (db_cont2) begin
    n_t_51x <= n_t_51x_m;
  end
always @(db_cont2, n3v, n_t_38x)
  if (~n3v) begin
    n_t_52x_m <= 1'b0;
  end else
  if (~(db_cont2)) begin
    n_t_52x_m <= n_t_38x;
  end
always @(db_cont2, n3v, n_t_52x_m)
  if (~n3v) begin
    n_t_52x <= 1'b0;
  end else
  if (db_cont2) begin
    n_t_52x <= n_t_52x_m;
  end
always @(db_cont2, n3v, n_t_32x)
  if (~n3v) begin
    n_t_53x_m <= 1'b0;
  end else
  if (~(db_cont2)) begin
    n_t_53x_m <= n_t_32x;
  end
always @(db_cont2, n3v, n_t_53x_m)
  if (~n3v) begin
    n_t_53x <= 1'b0;
  end else
  if (db_cont2) begin
    n_t_53x <= n_t_53x_m;
  end
always @(db_cont2, n3v, n_t_31x)
  if (~n3v) begin
    n_t_54x_m <= 1'b0;
  end else
  if (~(db_cont2)) begin
    n_t_54x_m <= n_t_31x;
  end
always @(db_cont2, n3v, n_t_54x_m)
  if (~n3v) begin
    n_t_54x <= 1'b0;
  end else
  if (db_cont2) begin
    n_t_54x <= n_t_54x_m;
  end
always @(db_cont2, n3v, n_t_30x)
  if (~n3v) begin
    n_t_55x_m <= 1'b0;
  end else
  if (~(db_cont2)) begin
    n_t_55x_m <= n_t_30x;
  end
always @(db_cont2, n3v, n_t_55x_m)
  if (~n3v) begin
    n_t_55x <= 1'b0;
  end else
  if (db_cont2) begin
    n_t_55x <= n_t_55x_m;
  end
always @(db_cont2, n3v, n_t_64x)
  if (~n3v) begin
    n_t_56x_m <= 1'b0;
  end else
  if (~(db_cont2)) begin
    n_t_56x_m <= n_t_64x;
  end
always @(db_cont2, n3v, n_t_56x_m)
  if (~n3v) begin
    n_t_56x <= 1'b0;
  end else
  if (db_cont2) begin
    n_t_56x <= n_t_56x_m;
  end
// e26: sn74h53 
// db4_ena = !(!ld_db_ac_l & btp3_ok
//          # data_state & write & n12th_bit_ok
//          # clr_all); 
// !db4_ena = !db4_ena; 
// e27: sn7404 
assign n_t_93x = ~idle;
assign n_t_101x = ~btp3;
// e28: sn7402 
assign n_t_42x = ~(wrt_brk_l
                    | ~db_cont2);
assign n_t_68x = ~(n_t_42x
                    | n_t_43x);
assign n_t_43x = ~(db_cont3
                    | rd_brk_l);
assign n_t_72x = ~(n_t_68x
                    | mak_l);
// e29: dec8235 
// c1_l = !(!n6rk5_l
//     # enab_rk_data); 
// c0_l = !(!n_t_35x
//     # n_t_3x); 
// e30: sp384n 
assign btp3 = tp3;
assign btp2 = tp2;
assign n_t_88x = busy_error
                  | crc_error;
// e31: sn7404 
assign n6rk7 = ~n6rk7_l;
// e32: sn7495 
always @(negedge (hi_wrt_clk & md_rd_buff_l
                       | ld_rd_buffer & ~md_rd_buff_l))
  if (~(hi_wrt_clk & md_rd_buff_l
                       | ld_rd_buffer & ~md_rd_buff_l)) begin
    n_t_32x <= bmd8 & ~md_rd_buff_l
                    | n_t_38x & md_rd_buff_l;
  end
always @(negedge (hi_wrt_clk & md_rd_buff_l
                       | ld_rd_buffer & ~md_rd_buff_l))
  if (~(hi_wrt_clk & md_rd_buff_l
                       | ld_rd_buffer & ~md_rd_buff_l)) begin
    n_t_31x <= bmd9 & ~md_rd_buff_l
                    | n_t_32x & md_rd_buff_l;
  end
always @(negedge (hi_wrt_clk & md_rd_buff_l
                       | ld_rd_buffer & ~md_rd_buff_l))
  if (~(hi_wrt_clk & md_rd_buff_l
                       | ld_rd_buffer & ~md_rd_buff_l)) begin
    n_t_30x <= bmd10 & ~md_rd_buff_l
                    | n_t_31x & md_rd_buff_l;
  end
always @(negedge (hi_wrt_clk & md_rd_buff_l
                       | ld_rd_buffer & ~md_rd_buff_l))
  if (~(hi_wrt_clk & md_rd_buff_l
                       | ld_rd_buffer & ~md_rd_buff_l)) begin
    n_t_64x <= bmd11 & ~md_rd_buff_l
                    | n_t_30x & md_rd_buff_l;
  end
// e33: sn7437 
assign n3v = 1'b1;
assign clr_all_l = ~clr_all;
assign clr_all = ~(n_t_78x & n_t_73x);
assign enab_rk_data = ~(wt_buff_data_l & ld_db_ac_l);
// e34: sn7402 
assign n_t_85x = ~(clr_all
                    | ld_cmd_reg);
assign n0_db4 = ~(test_clk
                   | clr_syn_l);
assign n_t_70x = ~(clr_all
                    | n_t_72x);
// e35: ds8640n 
assign n_t_78x = ~(~power_ok
                    | initialize);
assign b_io_pause = ~(ts3_l
                       | io_pause_l);
// e36: n8881n 
// skip_l = !(n_t_41x & !n6rk1_l); 
// int_rqst_l = !(n_t_41x & enab_int); 
// internal_io_l = !device_rk; 
// e37: dec8251 
assign n6rk1_l = ~(device_rk & ~bmd9 & ~bmd10 & bmd11);
assign n6rk2_l = ~(device_rk & ~bmd9 & bmd10 & ~bmd11);
assign n6rk3_l = ~(device_rk & ~bmd9 & bmd10 & bmd11);
assign n6rk4_l = ~(device_rk & bmd9 & ~bmd10 & ~bmd11);
assign n6rk5_l = ~(device_rk & bmd9 & ~bmd10 & bmd11);
assign n6rk6_l = ~(device_rk & bmd9 & bmd10 & ~bmd11);
assign n6rk7_l = ~(device_rk & bmd9 & bmd10 & bmd11);
// e38: sn74h74 
always @(btp2, main, n3v, data7_l)
  if (~main) begin
    ac7_m <= 1'b0;
  end else
  if (~n3v) begin
    ac7_m <= 1'b1;
  end else
  if (~(btp2)) begin
    ac7_m <= ~data7_l;
  end
always @(btp2, main, n3v, ac7_m)
  if (~main) begin
    ac7 <= 1'b0;
  end else
  if (~n3v) begin
    ac7 <= 1'b1;
  end else
  if (btp2) begin
    ac7 <= ac7_m;
  end
assign ac7_l = ~ac7;
always @(tp1, n_t_70x, n3v, brk_rq)
  if (~n_t_70x) begin
    b_brk_rq_m <= 1'b0;
  end else
  if (~n3v) begin
    b_brk_rq_m <= 1'b1;
  end else
  if (~(tp1)) begin
    b_brk_rq_m <= brk_rq;
  end
always @(tp1, n_t_70x, n3v, b_brk_rq_m)
  if (~n_t_70x) begin
    b_brk_rq <= 1'b0;
  end else
  if (~n3v) begin
    b_brk_rq <= 1'b1;
  end else
  if (tp1) begin
    b_brk_rq <= b_brk_rq_m;
  end
// e39: sn7474 
always @(data_clk_ok, clr_status_l, n_t_99x, db_cont4_l)
  if (~clr_status_l) begin
    data_rqst_late_m <= 1'b0;
  end else
  if (~n_t_99x) begin
    data_rqst_late_m <= 1'b1;
  end else
  if (~(data_clk_ok)) begin
    data_rqst_late_m <= db_cont4_l;
  end
always @(data_clk_ok, clr_status_l, n_t_99x, data_rqst_late_m)
  if (~clr_status_l) begin
    data_rqst_late <= 1'b0;
  end else
  if (~n_t_99x) begin
    data_rqst_late <= 1'b1;
  end else
  if (data_clk_ok) begin
    data_rqst_late <= data_rqst_late_m;
  end
always @(n_t_97x, n_t_98x, clr_status_l, 1'b0)
  if (~n_t_98x) begin
    done_flag_l_m <= 1'b0;
  end else
  if (~clr_status_l) begin
    done_flag_l_m <= 1'b1;
  end else
  if (~(n_t_97x)) begin
    done_flag_l_m <= 1'b0;
  end
always @(n_t_97x, n_t_98x, clr_status_l, done_flag_l_m)
  if (~n_t_98x) begin
    done_flag_l <= 1'b0;
  end else
  if (~clr_status_l) begin
    done_flag_l <= 1'b1;
  end else
  if (n_t_97x) begin
    done_flag_l <= done_flag_l_m;
  end
// e40: sn7408 
assign b_drive_status_er = (main_l & drive_status_er);
assign n_t_81x = (idle & n_t_82x);
assign n_t_35x = (n6rk3_l & ld_db_ac_l);
assign short_tp3 = (btp3 & n_t_102x);
// e41: sn7440 
assign n_t_73x = ~(btp3 & bdata10_l & ~n6rk2_l & bdata11);
assign n_t_80x = ~(n6rk3_l & n6rk6_l & n6rk4_l & n_t_79x);
// e42: ds8640n 
assign bmd10 = ~(md10_l
                  | md_rk_l);
assign bmd8 = ~md8_l;
assign bmd9 = ~(md9_l
                 | md_rk_l);
assign bmd11 = ~(md_rk_l
                  | md11_l);
// e43: sn74193 
always @(n3v, drv_revo, idle, n3v, n3v, gdollar_4)
  if (idle
                       | ~n3v & ~) begin
    gdollar_4_m <= 1'b0;
  end else
  if (~n3v & ) begin
    gdollar_4_m <= 1'b1;
  end else
  if (~(~(~n3v
                         | ~drv_revo))) begin
    gdollar_4_m <= ~gdollar_4;
  end
always @(n3v, drv_revo, idle, n3v, n3v, gdollar_4_m)
  if (idle
                       | ~n3v & ~) begin
    gdollar_4 <= 1'b0;
  end else
  if (~n3v & ) begin
    gdollar_4 <= 1'b1;
  end else
  if (~(~n3v
                         | ~drv_revo)) begin
    gdollar_4 <= gdollar_4_m;
  end
always @(n3v, gdollar_4, drv_revo, gdollar_4, idle, n3v, n3v, gdollar_5)
  if (idle
                       | ~n3v & ~) begin
    gdollar_5_m <= 1'b0;
  end else
  if (~n3v & ) begin
    gdollar_5_m <= 1'b1;
  end else
  if (~(~(~n3v & ~gdollar_4
                         | ~drv_revo & gdollar_4))) begin
    gdollar_5_m <= ~gdollar_5;
  end
always @(n3v, gdollar_4, drv_revo, gdollar_4, idle, n3v, n3v, gdollar_5_m)
  if (idle
                       | ~n3v & ~) begin
    gdollar_5 <= 1'b0;
  end else
  if (~n3v & ) begin
    gdollar_5 <= 1'b1;
  end else
  if (~(~n3v & ~gdollar_4
                         | ~drv_revo & gdollar_4)) begin
    gdollar_5 <= gdollar_5_m;
  end
always @(n3v, gdollar_4, gdollar_5, drv_revo, gdollar_4, gdollar_5, idle, n3v, n3v, gdollar_6)
  if (idle
                       | ~n3v & ~) begin
    gdollar_6_m <= 1'b0;
  end else
  if (~n3v & ) begin
    gdollar_6_m <= 1'b1;
  end else
  if (~(~(~n3v & ~gdollar_4 & ~gdollar_5
                         | ~drv_revo & gdollar_4 & gdollar_5))) begin
    gdollar_6_m <= ~gdollar_6;
  end
always @(n3v, gdollar_4, gdollar_5, drv_revo, gdollar_4, gdollar_5, idle, n3v, n3v, gdollar_6_m)
  if (idle
                       | ~n3v & ~) begin
    gdollar_6 <= 1'b0;
  end else
  if (~n3v & ) begin
    gdollar_6 <= 1'b1;
  end else
  if (~(~n3v & ~gdollar_4 & ~gdollar_5
                         | ~drv_revo & gdollar_4 & gdollar_5)) begin
    gdollar_6 <= gdollar_6_m;
  end
always @(n3v, gdollar_6, gdollar_4, gdollar_5, drv_revo, gdollar_6, gdollar_4, gdollar_5, idle, n3v, n3v, set_time_out_er)
  if (idle
                             | ~n3v & ~) begin
    set_time_out_er_m <= 1'b0;
  end else
  if (~n3v & ) begin
    set_time_out_er_m <= 1'b1;
  end else
  if (~(~(~n3v & ~gdollar_6 & ~gdollar_4 & ~gdollar_5
                               | ~drv_revo & gdollar_6 & gdollar_4 & gdollar_5))) begin
    set_time_out_er_m <= ~set_time_out_er;
  end
always @(n3v, gdollar_6, gdollar_4, gdollar_5, drv_revo, gdollar_6, gdollar_4, gdollar_5, idle, n3v, n3v, set_time_out_er_m)
  if (idle
                             | ~n3v & ~) begin
    set_time_out_er <= 1'b0;
  end else
  if (~n3v & ) begin
    set_time_out_er <= 1'b1;
  end else
  if (~(~n3v & ~gdollar_6 & ~gdollar_4 & ~gdollar_5
                               | ~drv_revo & gdollar_6 & gdollar_4 & gdollar_5)) begin
    set_time_out_er <= set_time_out_er_m;
  end
// e44: sn7440 
assign clr_drive_cmd_l = ~(bdata10 & bdata11_l & ~n6rk2_l & btp3_ok);
assign n_t_3x = ~(n6rk6_l & n6rk5_l & n6rk2_l & n6rk4_l);
// e45: sn7400 
assign n_t_79x = ~(~n6rk2_l & bdata11_l);
assign n_t_5x = ~(enable_status & drive_status_bad);
assign n_t_84x = ~(btp3_ok & ~n6rk2_l);
assign set_status_er = ~(dsk_capacity_ex_l & n_t_6x);
// e46: sn7400 
assign set_idle_pl_l = ~(n_t_10x & n_t_81x);
assign n_t_99x = ~(hi_rd_clk & db_cont1);
assign n_t_98x = ~(main & last_word_pl);
assign n_t_97x = ~(n_t_95x & set_idle_pl_l);
// e47: sn7410 
assign n_t_7x = ~(main_l & md_rd_buff_l & data_state_l);
assign n_t_95x = ~(rdy_s_r_w_slo & enab_seek_done & idle);
assign n_t_89x = ~(~data_rqst_late & n_t_87x & n_t_86x);
// e48: sn7408 
assign n_t_90x = (n_t_88x & idle);
assign clr_status_l = (n_t_85x & n_t_84x);
assign n_t_83x = (short_tp3 & idle_l);
assign set_busy_er = (n_t_80x & n_t_83x);
// e49: dec8235 
// data8_l = !(rk_data8 & enab_rk_data
//        # crc_error & !n6rk5_l); 
// data9_l = !(rk_data9 & enab_rk_data
//        # data_rqst_late & !n6rk5_l); 
// data10_l = !(rk_data10 & enab_rk_data
//         # drive_status_er & !n6rk5_l); 
// data11_l = !(rk_data11 & enab_rk_data
//         # cyl_addrs_er & !n6rk5_l); 
// e50: sn7496 
always @(n3v, n3v, clr_status_l, n3v, set_busy_er, 1'b1)
  if (~n3v & ~clr_status_l) begin
    busy_error_m <= 1'b0;
  end else
  if (n3v & set_busy_er) begin
    busy_error_m <= 1'b1;
  end else
  if (~(n3v)) begin
    busy_error_m <= 1'b1;
  end
always @(n3v, n3v, clr_status_l, n3v, set_busy_er, busy_error_m)
  if (~n3v & ~clr_status_l) begin
    busy_error <= 1'b0;
  end else
  if (n3v & set_busy_er) begin
    busy_error <= 1'b1;
  end else
  if (n3v) begin
    busy_error <= busy_error_m;
  end
always @(n3v, n3v, clr_status_l, n3v, set_crc_er, busy_error)
  if (~n3v & ~clr_status_l) begin
    crc_error_m <= 1'b0;
  end else
  if (n3v & set_crc_er) begin
    crc_error_m <= 1'b1;
  end else
  if (~(n3v)) begin
    crc_error_m <= busy_error;
  end
always @(n3v, n3v, clr_status_l, n3v, set_crc_er, crc_error_m)
  if (~n3v & ~clr_status_l) begin
    crc_error <= 1'b0;
  end else
  if (n3v & set_crc_er) begin
    crc_error <= 1'b1;
  end else
  if (n3v) begin
    crc_error <= crc_error_m;
  end
always @(n3v, n3v, clr_status_l, n3v, set_time_out_er, crc_error)
  if (~n3v & ~clr_status_l) begin
    time_out_er_m <= 1'b0;
  end else
  if (n3v & set_time_out_er) begin
    time_out_er_m <= 1'b1;
  end else
  if (~(n3v)) begin
    time_out_er_m <= crc_error;
  end
always @(n3v, n3v, clr_status_l, n3v, set_time_out_er, time_out_er_m)
  if (~n3v & ~clr_status_l) begin
    time_out_er <= 1'b0;
  end else
  if (n3v & set_time_out_er) begin
    time_out_er <= 1'b1;
  end else
  if (n3v) begin
    time_out_er <= time_out_er_m;
  end
always @(n3v, n3v, clr_status_l, n3v, set_status_er, time_out_er)
  if (~n3v & ~clr_status_l) begin
    drive_status_er_m <= 1'b0;
  end else
  if (n3v & set_status_er) begin
    drive_status_er_m <= 1'b1;
  end else
  if (~(n3v)) begin
    drive_status_er_m <= time_out_er;
  end
always @(n3v, n3v, clr_status_l, n3v, set_status_er, drive_status_er_m)
  if (~n3v & ~clr_status_l) begin
    drive_status_er <= 1'b0;
  end else
  if (n3v & set_status_er) begin
    drive_status_er <= 1'b1;
  end else
  if (n3v) begin
    drive_status_er <= drive_status_er_m;
  end
always @(n3v, n3v, clr_status_l, n3v, set_cyl_addrs_er, drive_status_er)
  if (~n3v & ~clr_status_l) begin
    cyl_addrs_er_m <= 1'b0;
  end else
  if (n3v & set_cyl_addrs_er) begin
    cyl_addrs_er_m <= 1'b1;
  end else
  if (~(n3v)) begin
    cyl_addrs_er_m <= drive_status_er;
  end
always @(n3v, n3v, clr_status_l, n3v, set_cyl_addrs_er, cyl_addrs_er_m)
  if (~n3v & ~clr_status_l) begin
    cyl_addrs_er <= 1'b0;
  end else
  if (n3v & set_cyl_addrs_er) begin
    cyl_addrs_er <= 1'b1;
  end else
  if (n3v) begin
    cyl_addrs_er <= cyl_addrs_er_m;
  end
// e51: sn7402 
assign md_rk_l = ~(~md_rd_buff_l
                    | b_io_pause);
assign set_crc_er = ~(not_equal_l
                       | end_state_l);
assign set_cyl_addrs_er = ~(not_equal_l
                             | sector_seek_l);
assign n_t_12x = ~(wrt_cmd_l
                    | dsk_wrt_status_l);
// e52: sn7474 
always @(ld_disk_addrs, clr_status_l, n3v, n_t_12x)
  if (~clr_status_l) begin
    wrt_lock_er_m <= 1'b0;
  end else
  if (~n3v) begin
    wrt_lock_er_m <= 1'b1;
  end else
  if (~(ld_disk_addrs)) begin
    wrt_lock_er_m <= n_t_12x;
  end
always @(ld_disk_addrs, clr_status_l, n3v, wrt_lock_er_m)
  if (~clr_status_l) begin
    wrt_lock_er <= 1'b0;
  end else
  if (~n3v) begin
    wrt_lock_er <= 1'b1;
  end else
  if (ld_disk_addrs) begin
    wrt_lock_er <= wrt_lock_er_m;
  end
always @(n_t_19x, n3v, db_cont4, 1'b0)
  if (~n3v) begin
    clr_syn_l_m <= 1'b0;
  end else
  if (~db_cont4) begin
    clr_syn_l_m <= 1'b1;
  end else
  if (~(n_t_19x)) begin
    clr_syn_l_m <= 1'b0;
  end
always @(n_t_19x, n3v, db_cont4, clr_syn_l_m)
  if (~n3v) begin
    clr_syn_l <= 1'b0;
  end else
  if (~db_cont4) begin
    clr_syn_l <= 1'b1;
  end else
  if (n_t_19x) begin
    clr_syn_l <= clr_syn_l_m;
  end
// e53: sn7402 
assign n_t_87x = ~(cyl_addrs_er
                    | b_drive_status_er);
assign n_t_86x = ~(wrt_lock_er
                    | time_out_er);
assign error_fl_l = ~(n_t_89x
                       | n_t_88x);
assign error_clr_l = ~(n_t_89x
                        | n_t_90x);
// e54: sn7400 
assign n_t_41x = ~(error_fl_l & done_flag_l);
assign enable_status = ~(clr_drive_cmd_l & ~ld_disk_addrs);
assign n_t_19x = ~(btp2 & ~wt_buff_data_l);
assign ld_db_ac_l = ~(ac7 & n6rk7);
// open collector 'wire-or's 
assign c0_l = (~n_t_35x
                | n_t_3x)? 1'b0: 1'bz;
assign c1_l = (~n6rk5_l
                | enab_rk_data)? 1'b0: 1'bz;
assign data0_l = (rk_data0 & enab_rk_data
                   | ~done_flag_l & ~n6rk5_l)? 1'b0: 1'bz;
assign data10_l = (rk_data10 & enab_rk_data
                    | drive_status_er & ~n6rk5_l)? 1'b0: 1'bz;
assign data11_l = (rk_data11 & enab_rk_data
                    | cyl_addrs_er & ~n6rk5_l)? 1'b0: 1'bz;
assign data1_l = (rk_data1 & enab_rk_data
                   | rdy_s_r_w_l & ~n6rk5_l)? 1'b0: 1'bz;
assign data2_l = (rk_data2 & enab_rk_data)? 1'b0: 1'bz;
assign data3_l = (rk_data3 & enab_rk_data
                   | seek_fail & ~n6rk5_l)? 1'b0: 1'bz;
assign data4_l = (rk_data4 & enab_rk_data
                   | dsk_file_rdy_l & ~n6rk5_l)? 1'b0: 1'bz;
assign data5_l = (rk_data5 & enab_rk_data
                   | busy_error & ~n6rk5_l)? 1'b0: 1'bz;
assign data6_l = (rk_data6 & enab_rk_data
                   | time_out_er & ~n6rk5_l)? 1'b0: 1'bz;
assign data7_l = (rk_data7 & enab_rk_data
                   | wrt_lock_er & ~n6rk5_l)? 1'b0: 1'bz;
assign data8_l = (rk_data8 & enab_rk_data
                   | crc_error & ~n6rk5_l)? 1'b0: 1'bz;
assign data9_l = (rk_data9 & enab_rk_data
                   | data_rqst_late & ~n6rk5_l)? 1'b0: 1'bz;
assign gdollar_0 = ~((n1_db2
                       | db4_ena & n1_db4
                       | n0_db4
                       | n1_db3));
assign db4_ena = ~((~ld_db_ac_l & btp3_ok
                     | data_state & write & n12th_bit_ok
                     | clr_all));
assign int_rqst_l = (n_t_41x & enab_int)? 1'b0: 1'bz;
assign internal_io_l = device_rk? ~device_rk: 1'bz;
assign skip_l = (n_t_41x & ~n6rk1_l)? 1'b0: 1'bz;
endmodule