~/Verilog/bin/topld.pl M7104B
info: cpol_use ne cpol_use20_8axial
info: cpol_use ne cpol_use20_8axial
info: cpol_use ne cpol_use20_8axial
info: 100ns ne rc_l_22
warning: making dl1/100ns/ a connector
info: sp314n ne dil14
info: 74174n ne dil16
info: 7402n ne dil14
info: 7476n ne dil16
info: ds8640n ne dil14
info: 7404n ne dil14
info: 7495n ne dil14
info: 74174n ne dil16
info: 7402n ne dil14
info: ds8640n ne dil14
info: 74h00n ne 7400n
info: 74h04n ne 7404n
info: dec8235 ne dil16
info: 7404n ne dil14
info: 7495n ne dil14
info: 74174n ne dil16
info: 74h53n ne dil14
info: 7404n ne dil14
info: 7402n ne dil14
info: dec8235 ne dil16
info: 7495n ne dil14
info: sp384n ne dil14
info: 7404n ne dil14
info: 7495n ne dil14
info: 7437n ne dil14
info: 7402n ne dil14
info: ds8640n ne dil14
info: n8881n ne dil14
info: dec8251 ne dil16
info: 74h74n ne 7474n
info: 74174n ne dil16
info: 7440n ne dil14
info: ds8640n ne dil14
info: 74193n ne dil16
info: 7440n ne dil14
info: 7400n ne dil14
info: 7400n ne dil14
info: 7410n ne dil14
info: dec8235 ne dil16
info: 7495n ne dil14
info: 7402n ne dil14
info: 7402n ne dil14
info: 7400n ne dil14
info: 74h53n ne dil14
info: 74123n ne dil16
warning: making e7/sn74123/ a connector
info: dec8235 ne dil16
info: 7495n ne dil14
info: edge_top ne edge_con2
warning: making h/edge_top/ a connector
info: edge_top ne edge_con2
warning: making j/edge_top/ a connector
info: quad ne edge_con8
warning: making omnibus/quad/ a connector
info: 0r2 ne 0r2/10
warning: making w1w4/0r2/ a connector
info: 0r2 ne 0r2/10
warning: making w2w5/0r2/ a connector
info: 0r2 ne 0r2/10
warning: making w3w6/0r2/ a connector
warning: non-bypass capacitor deleted: c47
warning: non-bypass capacitor deleted: c48
warning: non-bypass capacitor deleted: c49
warning: non-bypass capacitor deleted: c50
warning: non-bypass capacitor deleted: c51
warning: non-bypass capacitor deleted: c52
warning: non-bypass capacitor deleted: c56
~/Verilog/bin/smaller.pl M7104B.PLD >vv || (rm vv; exit 1)
35 signals were removed:
  b_io_pause_l: !b_io_pause
  btp1: tp1
  data_rqst_late_l: !data_rqst_late
  db_cont2_l: !db_cont2
  db_cont3_l: !db_cont3
  device_rk_l: !device_rk
  done_flag: !done_flag_l
  enab_rk_data_l: !enab_rk_data
  gdollar_1: !gdollar_0
  gdollar_2: db4_ena
  gdollar_3: !gdollar_2
  hi_rd_clk_l: !hi_rd_clk
  ld_db_ac: !ld_db_ac_l
  md_rd_buff: !md_rd_buff_l
  n6rk1: !n6rk1_l
  n6rk2: !n6rk2_l
  n_t_100x: !ld_disk_addrs
  n_t_15x: !n_t_14x
  n_t_71x: !data7_l
  n_t_77x: !power_ok
  rk_data0_l: !rk_data0
  rk_data10_l: !rk_data10
  rk_data11_l: !rk_data11
  rk_data1_l: !rk_data1
  rk_data2_l: !rk_data2
  rk_data3_l: !rk_data3
  rk_data4_l: !rk_data4
  rk_data5_l: !rk_data5
  rk_data6_l: !rk_data6
  rk_data7_l: !rk_data7
  rk_data8_l: !rk_data8
  rk_data9_l: !rk_data9
  wrt_buf_data: !wt_buff_data_l
  wrt_buff_shft_l: !wrt_buff_shft
  wrt_lock_er_l: !wrt_lock_er
~/Verilog/bin/smaller.pl vv >M7104BX.PLD || (rm M7104BX.PLD; exit 1)
1 signals were removed:
  gdollar_2: db4_ena
~/Verilog/bin/cupl2v.pl M7104BX.PLD >vv || (rm vv; exit 1)
mv vv M7104B.v
rm M7104BX.PLD