/* This file is generated by topld.pl!! */ /* Please don't edit it. */ Name M7105B ; PartNo cpld ; Date XX/XX/XXXX ; Revision 01 ; Designer ; Company ; Assembly None ; Location E1 ; Device f1508isptqfp100; $DEFINE OPTIMIZE $UNDEF OPTIMIZE /* Input Pins */ pin = ac7_l; pin = b_brk_rq; pin = b_last_brk; pin = bdata10; pin = bdata11; pin = bdata8; pin = bdata9; pin = brk_enab_clk; pin = brk_in_clk; pin = btp3_l; pin = btp3_ok; pin = clr_all; pin = clr_all_l; pin = clr_cntrs_l; pin = crc_data; pin = data_in_l; pin = data_state_l; pin = db_cont1_l; pin = db_cont4; pin = device_rk; pin = dsk_rdy_s_r_w_l; pin = dsk_seek_fail_l; pin = file_rdy; pin = idle; pin = idle_l; pin = ld_disk_addrs; pin = n6rk3_ok_l; pin = n6rk4_l; pin = n6rk6; pin = n6rk7; pin = n6rk7_ok; pin = n_t_27x; pin = n_t_31x; pin = n_t_8x; pin = rd_clk1; pin = rd_shft_db_l; pin = sector_addrs_1; pin = shift_crc_l; pin = state_enab_b; pin = strobe; pin = wrt_cmd_l; /* Output Pins */ pin = b_data_state; pin = bdata1; pin = bdata10_l; pin = bdata11_l; pin = bdata7; pin = bk_cycle_l; pin = brk_dir_l; pin = brk_in_prog_l; pin = brk_rq; pin = clr_sector_ad_l; pin = cpma_dis_l; pin = crc16; pin = data0_l; pin = data1_l; pin = data2_l; pin = data3_l; pin = data4_l; pin = data5_l; pin = data6_l; pin = data7_l; pin = data_enab_l; pin = data_enable; pin = drive_status_bad; pin = dsk_cyl_ad128_l; pin = dsk_cyl_ad16_l; pin = dsk_cyl_ad1_l; pin = dsk_cyl_ad2_l; pin = dsk_cyl_ad32_l; pin = dsk_cyl_ad4_l; pin = dsk_cyl_ad64_l; pin = dsk_cyl_ad8_l; pin = dsk_drive0_l; pin = dsk_drive1_l; pin = dsk_drive2_l; pin = dsk_drive3_l; pin = ema0_l; pin = ema1_l; pin = ema2_l; pin = enab_int; pin = enab_seek_done; pin = function00; pin = function01; pin = function02; pin = half_block; pin = hi_data_in; pin = hi_main_shft_l; pin = hi_rd_clk; pin = int_strobe; pin = last_brk; pin = ld_cmd_reg; pin = lo_main_data; pin = lo_main_shft_l; pin = ma0_l; pin = ma10_l; pin = ma11_l; pin = ma1_l; pin = ma2_l; pin = ma3_l; pin = ma4_l; pin = ma5_l; pin = ma6_l; pin = ma7_l; pin = ma8_l; pin = ma9_l; pin = main; pin = main_l; pin = main_pl; pin = mak_l; pin = mams_load_cont_l; pin = md_dir_l; pin = msir_dis_l; pin = n_t_30x; pin = n_t_4x; pin = not_equal_l; pin = priority; pin = rd_brk_l; pin = rdy_s_r_w; pin = rdy_s_r_w_l; pin = seek_fail; pin = shft_surf; pin = tp1; pin = tp4; pin = ts2; pin = ts4; pin = wrt_brk_l; pin = wt_buff_data_l; node ema0; node ema1; node crc9; node crc10; node crc11; node crc12; node crc13; node n_t_39x; node n_t_38x; node n_t_37x; node n_t_26x; node crc4; node crc5; node crc6; node crc7; node crc8; node ema2; node unit_sel0; node unit_sel1; node ext_cyl_addrs; node n_t_47x; node n_t_44x; node n_t_45x; node n_t_42x; node n_t_48x; node n_t_41x; node n_t_43x; node n_t_40x; node crc1; node crc2; node crc3; node crc14; node crc15; node malc; node not_equal; node brk_dir; node nbr; node mak; node brk_enable_l; node brk_in_l; /* Internal nodes */ $IFNDEF OPTIMIZE node bdata0; node bdata2; node bdata2_l; node bdata3; node bdata4; node bdata5; node bdata6; node bint_strobe; node brk_enable; node brk_in; node btp1; node btp4; node bts2; node bts4; node clr_dsk_ad_l; node crc_main_data_l; node crc_main_shft_l; node data_enable_l; node disk_priority; node drive0_l; node drive1_l; node drive2_l; node drive3_l; node hi_main_data_l; node last_brk_l; node ld_shft_cmd_reg_l; node mad; node main_data; node main_enab; node malc_l; node mux_input; node n3v; node n_t_10x; node n_t_11x; node n_t_12x; node n_t_13x; node n_t_14x; node n_t_15x; node n_t_16x; node n_t_17x; node n_t_18x; node n_t_19x; node n_t_1x; node n_t_20x; node n_t_21x; node n_t_22x; node n_t_23x; node n_t_24x; node n_t_25x; node n_t_29x; node n_t_2x; node n_t_32x; node n_t_33x; node n_t_34x; node n_t_35x; node n_t_3x; node n_t_49x; node n_t_55x; node n_t_5x; node n_t_6x; node n_t_7x; node n_t_9x; node nbr_l; node set_main_brk; node set_main_brk_l; node shft_cmd_reg; node start_clr_l; $ENDIF /* Code nodes */ /* Equations */ /* c1: c_us */ /* c2: c_us */ /* c3: c_us */ /* c4: c_us */ /* c5: c_us */ /* c6: c_us */ /* c7: c_us */ /* c8: c_us */ /* c9: c_us */ /* c10: c_us */ /* c11: c_us */ /* c12: c_us */ /* c13: c_us */ /* c14: c_us */ /* c15: c_us */ /* c16: c_us */ /* c17: c_us */ /* c18: c_us */ /* c19: c_us */ /* c20: c_us */ /* c21: c_us */ /* c22: c_us */ /* c23: c_us */ /* c24: c_us */ /* c25: c_us */ /* c26: c_us */ /* c27: c_us */ /* c28: c_us */ /* c29: c_us */ /* c30: c_us */ /* c31: c_us */ /* c32: c_us */ /* c33: c_us */ /* c34: cpol_use */ /* c35: cpol_use */ /* c36: cpol_use */ /* c37: c_us */ /* e1: n8881n */ /* ema2_l = !(ema2 & data_enable); */ /* ema1_l = !(ema1 & data_enable); */ /* ema0_l = !(data_enable & ema0); */ /* md_dir_l = !(data_enable & brk_dir_l); */ /* e2: dec8271 */ function00.ar = !clr_all_l; function00.d = bdata0 & n6rk6 & !n6rk7 # function00 & !n6rk6 & !n6rk7; function00.ck = !ld_shft_cmd_reg_l; function01.ar = !clr_all_l; function01.d = function00 & n6rk7 # bdata1 & n6rk6 & !n6rk7 # function01 & !n6rk6 & !n6rk7; function01.ck = !ld_shft_cmd_reg_l; function02.ar = !clr_all_l; function02.d = function01 & n6rk7 # bdata2 & n6rk6 & !n6rk7 # function02 & !n6rk6 & !n6rk7; function02.ck = !ld_shft_cmd_reg_l; enab_int.ar = !clr_all_l; enab_int.d = function02 & n6rk7 # bdata3 & n6rk6 & !n6rk7 # enab_int & !n6rk6 & !n6rk7; enab_int.ck = !ld_shft_cmd_reg_l; /* e3: dec8271 */ enab_seek_done.ar = !clr_all_l; enab_seek_done.d = enab_int & n6rk7 # bdata4 & n6rk6 & !n6rk7 # enab_seek_done & !n6rk6 & !n6rk7; enab_seek_done.ck = !ld_shft_cmd_reg_l; half_block.ar = !clr_all_l; half_block.d = enab_seek_done & n6rk7 # bdata5 & n6rk6 & !n6rk7 # half_block & !n6rk6 & !n6rk7; half_block.ck = !ld_shft_cmd_reg_l; ema0.ar = !clr_all_l; ema0.d = half_block & n6rk7 # bdata6 & n6rk6 & !n6rk7 # ema0 & !n6rk6 & !n6rk7; ema0.ck = !ld_shft_cmd_reg_l; ema1.ar = !clr_all_l; ema1.d = ema0 & n6rk7 # bdata7 & n6rk6 & !n6rk7 # ema1 & !n6rk6 & !n6rk7; ema1.ck = !ld_shft_cmd_reg_l; /* e4: sn7496 */ crc9.ck = n_t_2x; crc9.d = crc8; crc9.ap = ld_disk_addrs & bdata4; crc9.ar = !ld_disk_addrs & !clr_dsk_ad_l; crc10.ck = n_t_2x; crc10.d = crc9; crc10.ap = ld_disk_addrs & bdata5; crc10.ar = !ld_disk_addrs & !clr_dsk_ad_l; crc11.ck = n_t_2x; crc11.d = crc10; crc11.ap = ld_disk_addrs & bdata6; crc11.ar = !ld_disk_addrs & !clr_dsk_ad_l; crc12.ck = n_t_2x; crc12.d = crc11; crc12.ap = 'b'0; crc12.ar = !ld_disk_addrs & !clr_dsk_ad_l; crc13.ck = n_t_2x; crc13.d = crc12; crc13.ap = 'b'0; crc13.ar = !ld_disk_addrs & !clr_dsk_ad_l; /* e5: ds75452n */ /* dsk_cyl_ad1_l = !(!(crc11 & strobe)); */ /* dsk_cyl_ad8_l = !(!(crc8 & strobe)); */ /* e6: ds75452n */ /* dsk_cyl_ad4_l = !(!(strobe & crc9)); */ /* dsk_cyl_ad2_l = !(!(crc10 & strobe)); */ /* e7: n8881n */ /* ma3_l = !(n_t_39x & mak); */ /* ma2_l = !(n_t_38x & mak); */ /* ma1_l = !(mak & n_t_37x); */ /* ma0_l = !(mak & n_t_26x); */ /* e8: sn74161 */ n_t_39x.ar = !clr_all_l; n_t_39x.ck = !n_t_29x; n_t_39x.j = !(!bdata3 & !n6rk4_l) & (n_t_19x # !n6rk4_l); n_t_39x.k = !(bdata3 & !n6rk4_l) & (n_t_19x # !n6rk4_l); n_t_38x.ar = !clr_all_l; n_t_38x.ck = !n_t_29x; n_t_38x.j = !(!bdata2 & !n6rk4_l) & ((n_t_19x & n_t_39x) # !n6rk4_l); n_t_38x.k = !(bdata2 & !n6rk4_l) & ((n_t_19x & n_t_39x) # !n6rk4_l); n_t_37x.ar = !clr_all_l; n_t_37x.ck = !n_t_29x; n_t_37x.j = !(!bdata1 & !n6rk4_l) & ((n_t_19x & n_t_39x & n_t_38x) # !n6rk4_l); n_t_37x.k = !(bdata1 & !n6rk4_l) & ((n_t_19x & n_t_39x & n_t_38x) # !n6rk4_l); n_t_26x.ar = !clr_all_l; n_t_26x.ck = !n_t_29x; n_t_26x.j = !(!bdata0 & !n6rk4_l) & ((n_t_19x & n_t_39x & n_t_38x & n_t_37x) # !n6rk4_l); n_t_26x.k = !(bdata0 & !n6rk4_l) & ((n_t_19x & n_t_39x & n_t_38x & n_t_37x) # !n6rk4_l); /* e9: sn7452 */ n_t_1x = ext_cyl_addrs & bdata3 # bdata4 & sector_addrs_1 # bdata2 & crc16; /* e10: sn74155 */ drive0_l = !(!unit_sel0 & !unit_sel1 & !ld_cmd_reg & n3v); drive1_l = !(!unit_sel0 & unit_sel1 & !ld_cmd_reg & n3v); drive2_l = !(unit_sel0 & !unit_sel1 & !ld_cmd_reg & n3v); drive3_l = !(unit_sel0 & unit_sel1 & !ld_cmd_reg & n3v); /* e11: ds75451n */ /* dsk_drive1_l = !drive1_l; */ /* dsk_drive0_l = !drive0_l; */ /* e12: ds75451n */ /* dsk_drive3_l = !drive3_l; */ /* dsk_drive2_l = !drive2_l; */ /* e13: sp380n */ !bdata3 = data_enab_l # data3_l; !bdata2 = data2_l # data_enab_l; !bdata0 = data_enab_l # data0_l; !bdata1 = data_enab_l # data1_l; /* e14: sn7496 */ crc4.ck = n_t_2x; crc4.d = crc3; crc4.ap = ld_disk_addrs & ext_cyl_addrs; crc4.ar = !ld_disk_addrs & !clr_dsk_ad_l; crc5.ck = n_t_2x; crc5.d = crc4; crc5.ap = ld_disk_addrs & bdata0; crc5.ar = !ld_disk_addrs & !clr_dsk_ad_l; crc6.ck = n_t_2x; crc6.d = crc5; crc6.ap = ld_disk_addrs & bdata1; crc6.ar = !ld_disk_addrs & !clr_dsk_ad_l; crc7.ck = n_t_2x; crc7.d = crc6; crc7.ap = ld_disk_addrs & bdata2; crc7.ar = !ld_disk_addrs & !clr_dsk_ad_l; crc8.ck = n_t_2x; crc8.d = crc7; crc8.ap = ld_disk_addrs & bdata3; crc8.ar = !ld_disk_addrs & !clr_dsk_ad_l; /* e15: ds75452n */ /* dsk_cyl_ad16_l = !(!(strobe & crc7)); */ /* dsk_cyl_ad32_l = !(!(strobe & crc6)); */ /* e16: ds75452n */ /* dsk_cyl_ad128_l = !(!(strobe & crc4)); */ /* dsk_cyl_ad64_l = !(!(crc5 & strobe)); */ /* e17: dec8271 */ ema2.ar = !clr_all_l; ema2.d = ema1 & n6rk7 # bdata8 & n6rk6 & !n6rk7 # ema2 & !n6rk6 & !n6rk7; ema2.ck = !ld_shft_cmd_reg_l; unit_sel0.ar = !clr_all_l; unit_sel0.d = ema2 & n6rk7 # bdata9 & n6rk6 & !n6rk7 # unit_sel0 & !n6rk6 & !n6rk7; unit_sel0.ck = !ld_shft_cmd_reg_l; unit_sel1.ar = !clr_all_l; unit_sel1.d = unit_sel0 & n6rk7 # bdata10 & n6rk6 & !n6rk7 # unit_sel1 & !n6rk6 & !n6rk7; unit_sel1.ck = !ld_shft_cmd_reg_l; ext_cyl_addrs.ar = !clr_all_l; ext_cyl_addrs.d = unit_sel1 & n6rk7 # bdata11 & n6rk6 & !n6rk7 # ext_cyl_addrs & !n6rk6 & !n6rk7; ext_cyl_addrs.ck = !ld_shft_cmd_reg_l; /* e18: sn74161 */ n_t_47x.ar = !clr_all_l; n_t_47x.ck = !n_t_29x; n_t_47x.j = !(!bdata11 & !n6rk4_l) & (n3v # !n6rk4_l); n_t_47x.k = !(bdata11 & !n6rk4_l) & (n3v # !n6rk4_l); n_t_44x.ar = !clr_all_l; n_t_44x.ck = !n_t_29x; n_t_44x.j = !(!bdata10 & !n6rk4_l) & ((n3v & n_t_47x) # !n6rk4_l); n_t_44x.k = !(bdata10 & !n6rk4_l) & ((n3v & n_t_47x) # !n6rk4_l); n_t_45x.ar = !clr_all_l; n_t_45x.ck = !n_t_29x; n_t_45x.j = !(!bdata9 & !n6rk4_l) & ((n3v & n_t_47x & n_t_44x) # !n6rk4_l); n_t_45x.k = !(bdata9 & !n6rk4_l) & ((n3v & n_t_47x & n_t_44x) # !n6rk4_l); n_t_42x.ar = !clr_all_l; n_t_42x.ck = !n_t_29x; n_t_42x.j = !(!bdata8 & !n6rk4_l) & ((n3v & n_t_47x & n_t_44x & n_t_45x) # !n6rk4_l); n_t_42x.k = !(bdata8 & !n6rk4_l) & ((n3v & n_t_47x & n_t_44x & n_t_45x) # !n6rk4_l); n_t_18x = n3v & n_t_42x & n_t_45x & n_t_44x & n_t_47x; /* e19: sn74h00 */ clr_sector_ad_l = !(n_t_9x & idle); drive_status_bad = !(file_rdy & rdy_s_r_w); /* e20: n8881n */ /* ma7_l = !(mak & n_t_48x); */ /* ma6_l = !(n_t_41x & mak); */ /* ma4_l = !(mak & n_t_40x); */ /* ma5_l = !(mak & n_t_43x); */ /* e21: sn74161 */ n_t_48x.ar = !clr_all_l; n_t_48x.ck = !n_t_29x; n_t_48x.j = !(!bdata7 & !n6rk4_l) & (n_t_18x # !n6rk4_l); n_t_48x.k = !(bdata7 & !n6rk4_l) & (n_t_18x # !n6rk4_l); n_t_41x.ar = !clr_all_l; n_t_41x.ck = !n_t_29x; n_t_41x.j = !(!bdata6 & !n6rk4_l) & ((n_t_18x & n_t_48x) # !n6rk4_l); n_t_41x.k = !(bdata6 & !n6rk4_l) & ((n_t_18x & n_t_48x) # !n6rk4_l); n_t_43x.ar = !clr_all_l; n_t_43x.ck = !n_t_29x; n_t_43x.j = !(!bdata5 & !n6rk4_l) & ((n_t_18x & n_t_48x & n_t_41x) # !n6rk4_l); n_t_43x.k = !(bdata5 & !n6rk4_l) & ((n_t_18x & n_t_48x & n_t_41x) # !n6rk4_l); n_t_40x.ar = !clr_all_l; n_t_40x.ck = !n_t_29x; n_t_40x.j = !(!bdata4 & !n6rk4_l) & ((n_t_18x & n_t_48x & n_t_41x & n_t_43x) # !n6rk4_l); n_t_40x.k = !(bdata4 & !n6rk4_l) & ((n_t_18x & n_t_48x & n_t_41x & n_t_43x) # !n6rk4_l); n_t_19x = n_t_18x & n_t_40x & n_t_43x & n_t_41x & n_t_48x; /* e22: sp380n */ !bdata6 = data6_l # data_enab_l; !bdata7 = data_enab_l # data7_l; !bdata5 = data5_l # data_enab_l; !bdata4 = data_enab_l # data4_l; /* e23: sn74174 */ crc1.ar = !clr_dsk_ad_l; crc1.ck = n_t_2x; crc1.d = n_t_21x; crc2.ar = !clr_dsk_ad_l; crc2.ck = n_t_2x; crc2.d = crc1; crc3.ar = !clr_dsk_ad_l; crc3.ck = n_t_2x; crc3.d = n_t_20x; crc14.ar = !clr_dsk_ad_l; crc14.ck = n_t_2x; crc14.d = crc13; crc15.ar = !clr_dsk_ad_l; crc15.ck = n_t_2x; crc15.d = crc14; crc16.ar = !clr_dsk_ad_l; crc16.ck = n_t_2x; crc16.d = n_t_17x; /* e24: sn7486 */ n_t_9x = clr_dsk_ad_l $ n3v; n_t_20x = n_t_10x $ crc2; n_t_6x = crc_data $ crc16; n_t_17x = crc15 $ n_t_12x; /* e25: sn7408 */ n_t_13x = (clr_cntrs_l & start_clr_l); main_pl = (main_enab & n6rk7_ok); n_t_14x = (rd_clk1 & state_enab_b); shft_surf = (main_pl & bdata4); /* e26: n8881n */ /* bk_cycle_l = !data_enable; */ /* msir_dis_l = !data_enable; */ /* brk_in_prog_l = !nbr; */ /* mams_load_cont_l = !malc; */ /* e27: sp384n */ btp1 = tp1; bint_strobe = int_strobe; /* e28: sn7402 */ n_t_49x = !(clr_all # btp1); n_t_22x = !(n_t_24x # btp4); start_clr_l = !(ld_disk_addrs # clr_all); n_t_29x = !(n_t_22x # n_t_23x); /* e29: sn7400 */ n_t_5x = !(b_data_state & n_t_6x); n_t_3x = !(data_state_l & mux_input); n_t_21x = !(n_t_3x & n_t_5x); clr_dsk_ad_l = !(n_t_7x & n_t_8x); /* e30: sn7408 */ n_t_10x = (b_data_state & n_t_6x); main_enab = (ac7_l & main); lo_main_data = (n_t_1x & main); n_t_12x = (n_t_6x & b_data_state); /* e31: sn7400 */ n_t_16x = !(n_t_11x & bdata2_l); lo_main_shft_l = !(main_pl & n_t_16x); n_t_2x = !(shift_crc_l & crc_main_shft_l); mux_input = !(crc_main_data_l & data_in_l); /* e32: sp380n */ !bts2 = ts2; !bts4 = ts4; !rdy_s_r_w = dsk_rdy_s_r_w_l; !n_t_30x = n_t_31x; /* e33: sn74h11 */ mad = disk_priority & nbr & n3v; btp4 = n3v & tp4; n_t_55x = btp4 & n_t_34x & n3v; /* e34: sn74h74 */ malc.ar = !clr_all_l; malc.d = data_enable; malc.ck = btp1; malc.ap = !n3v; malc_l = !malc; not_equal.ar = !n_t_13x; not_equal.d = n_t_6x; not_equal.ck = n_t_14x; not_equal.ap = !not_equal_l; not_equal_l = !not_equal; /* e35: sn7474 */ brk_dir.ar = !clr_all_l; brk_dir.d = brk_in; brk_dir.ck = btp1; brk_dir.ap = !n3v; brk_dir_l = !brk_dir; nbr.ar = !n_t_49x; nbr.d = b_brk_rq; nbr.ck = bint_strobe; nbr.ap = !n3v; nbr_l = !nbr; /* e36: sn7400 */ n_t_34x = !(data_enable_l & nbr_l); brk_rq = !(wrt_brk_l & rd_brk_l); n_t_32x = !(set_main_brk & wrt_cmd_l); set_main_brk_l = !(main_pl & bdata6); /* e37: sn74h10 */ hi_main_shft_l = !(bdata5 & main_enab & n6rk7_ok); rd_brk_l = !(db_cont4 & brk_enable & brk_in); wt_buff_data_l = !(data_enable & brk_dir & bts2); /* e38: n8881n */ /* data_enab_l = !device_rk; */ /* cpma_dis_l = !nbr; */ /* priority = !(nbr & bts4); */ /* e39: sn74h74 */ main.ar = !clr_all_l; main.d = bdata0; main.ck = n6rk7_ok; main.ap = !main_l; main_l = !main; data_enable.ar = !clr_all_l; data_enable.d = mad; data_enable.ck = n_t_55x; data_enable.ap = !n3v; data_enable_l = !data_enable; /* e40: sn7400 */ crc_main_data_l = !(main_data & bdata2); crc_main_shft_l = !(bdata2 & main_pl); n_t_35x = !(mak & main); n_t_24x = !(bts4 & data_enable); /* e41: sn7408 */ shft_cmd_reg = (main_pl & bdata3); ld_cmd_reg = (btp3_ok & n6rk6); n_t_23x = (n_t_25x & btp3_l); n_t_33x = (n_t_35x & start_clr_l); /* e42: sn7404 */ n3v = 'b'1; seek_fail = !dsk_seek_fail_l; disk_priority = !n_t_27x; b_data_state = !data_state_l; set_main_brk = !set_main_brk_l; /* e43: sn7404 */ n_t_4x = !n_t_7x; n_t_15x = !b_last_brk; bdata2_l = !bdata2; rdy_s_r_w_l = !rdy_s_r_w; bdata11_l = !bdata11; bdata10_l = !bdata10; /* e44: n8881n */ /* ma10_l = !(n_t_44x & mak); */ /* ma9_l = !(n_t_45x & mak); */ /* ma8_l = !(n_t_42x & mak); */ /* ma11_l = !(mak & n_t_47x); */ /* e45: sn74h74 */ mak.ar = !clr_all_l; mak.d = mad; mak.ck = n_t_55x; mak.ap = !n3v; mak_l = !mak; last_brk.ar = !start_clr_l; last_brk.d = n3v; last_brk.ck = n_t_15x; last_brk.ap = !n3v; last_brk_l = !last_brk; /* e46: sn7440 */ wrt_brk_l = !(last_brk_l & brk_enable & brk_in_l & db_cont1_l); /* e47: sn7402 */ n_t_11x = !(bdata3 # bdata4); ld_shft_cmd_reg_l = !(shft_cmd_reg # ld_cmd_reg); main_data = !(bdata10_l # main_l); n_t_25x = !(n6rk4_l # idle_l); /* e48: sn74h74 */ brk_enable_l.ar = !set_main_brk_l; brk_enable_l.d = 'b'0; brk_enable_l.ck = brk_enab_clk; brk_enable_l.ap = !n_t_33x; brk_enable = !brk_enable_l; brk_in_l.ar = !n_t_32x; brk_in_l.d = 'b'0; brk_in_l.ck = brk_in_clk; brk_in_l.ap = !start_clr_l; brk_in = !brk_in_l; /* e49: sn7400 */ hi_main_data_l = !(main_data & bdata5); n_t_7x = !(n6rk3_ok_l & data_state_l); hi_rd_clk = !(rd_shft_db_l & hi_main_shft_l); hi_data_in = !(hi_main_data_l & data_in_l); /* Open collector 'wire-or's */ property atmel {open_collector= bk_cycle_l}; !bk_cycle_l = data_enable; bk_cycle_l.oe = data_enable; property atmel {open_collector= brk_in_prog_l}; !brk_in_prog_l = nbr; brk_in_prog_l.oe = nbr; property atmel {open_collector= cpma_dis_l}; !cpma_dis_l = nbr; cpma_dis_l.oe = nbr; property atmel {open_collector= data_enab_l}; !data_enab_l = device_rk; data_enab_l.oe = device_rk; property atmel {open_collector= dsk_cyl_ad128_l}; !dsk_cyl_ad128_l = (!(strobe & crc4)); dsk_cyl_ad128_l.oe = (!(strobe & crc4)); property atmel {open_collector= dsk_cyl_ad16_l}; !dsk_cyl_ad16_l = (!(strobe & crc7)); dsk_cyl_ad16_l.oe = (!(strobe & crc7)); property atmel {open_collector= dsk_cyl_ad1_l}; !dsk_cyl_ad1_l = (!(crc11 & strobe)); dsk_cyl_ad1_l.oe = (!(crc11 & strobe)); property atmel {open_collector= dsk_cyl_ad2_l}; !dsk_cyl_ad2_l = (!(crc10 & strobe)); dsk_cyl_ad2_l.oe = (!(crc10 & strobe)); property atmel {open_collector= dsk_cyl_ad32_l}; !dsk_cyl_ad32_l = (!(strobe & crc6)); dsk_cyl_ad32_l.oe = (!(strobe & crc6)); property atmel {open_collector= dsk_cyl_ad4_l}; !dsk_cyl_ad4_l = (!(strobe & crc9)); dsk_cyl_ad4_l.oe = (!(strobe & crc9)); property atmel {open_collector= dsk_cyl_ad64_l}; !dsk_cyl_ad64_l = (!(crc5 & strobe)); dsk_cyl_ad64_l.oe = (!(crc5 & strobe)); property atmel {open_collector= dsk_cyl_ad8_l}; !dsk_cyl_ad8_l = (!(crc8 & strobe)); dsk_cyl_ad8_l.oe = (!(crc8 & strobe)); property atmel {open_collector= dsk_drive0_l}; !dsk_drive0_l = drive0_l; dsk_drive0_l.oe = drive0_l; property atmel {open_collector= dsk_drive1_l}; !dsk_drive1_l = drive1_l; dsk_drive1_l.oe = drive1_l; property atmel {open_collector= dsk_drive2_l}; !dsk_drive2_l = drive2_l; dsk_drive2_l.oe = drive2_l; property atmel {open_collector= dsk_drive3_l}; !dsk_drive3_l = drive3_l; dsk_drive3_l.oe = drive3_l; property atmel {open_collector= ema0_l}; !ema0_l = (data_enable & ema0); ema0_l.oe = (data_enable & ema0); property atmel {open_collector= ema1_l}; !ema1_l = (ema1 & data_enable); ema1_l.oe = (ema1 & data_enable); property atmel {open_collector= ema2_l}; !ema2_l = (ema2 & data_enable); ema2_l.oe = (ema2 & data_enable); property atmel {open_collector= ma0_l}; !ma0_l = (mak & n_t_26x); ma0_l.oe = (mak & n_t_26x); property atmel {open_collector= ma10_l}; !ma10_l = (n_t_44x & mak); ma10_l.oe = (n_t_44x & mak); property atmel {open_collector= ma11_l}; !ma11_l = (mak & n_t_47x); ma11_l.oe = (mak & n_t_47x); property atmel {open_collector= ma1_l}; !ma1_l = (mak & n_t_37x); ma1_l.oe = (mak & n_t_37x); property atmel {open_collector= ma2_l}; !ma2_l = (n_t_38x & mak); ma2_l.oe = (n_t_38x & mak); property atmel {open_collector= ma3_l}; !ma3_l = (n_t_39x & mak); ma3_l.oe = (n_t_39x & mak); property atmel {open_collector= ma4_l}; !ma4_l = (mak & n_t_40x); ma4_l.oe = (mak & n_t_40x); property atmel {open_collector= ma5_l}; !ma5_l = (mak & n_t_43x); ma5_l.oe = (mak & n_t_43x); property atmel {open_collector= ma6_l}; !ma6_l = (n_t_41x & mak); ma6_l.oe = (n_t_41x & mak); property atmel {open_collector= ma7_l}; !ma7_l = (mak & n_t_48x); ma7_l.oe = (mak & n_t_48x); property atmel {open_collector= ma8_l}; !ma8_l = (n_t_42x & mak); ma8_l.oe = (n_t_42x & mak); property atmel {open_collector= ma9_l}; !ma9_l = (n_t_45x & mak); ma9_l.oe = (n_t_45x & mak); property atmel {open_collector= mams_load_cont_l}; !mams_load_cont_l = malc; mams_load_cont_l.oe = malc; property atmel {open_collector= md_dir_l}; !md_dir_l = (data_enable & brk_dir_l); md_dir_l.oe = (data_enable & brk_dir_l); property atmel {open_collector= msir_dis_l}; !msir_dis_l = data_enable; msir_dis_l.oe = data_enable; property atmel {open_collector= priority}; !priority = (nbr & bts4); priority.oe = (nbr & bts4);