// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// c5: c_us 
// c6: c_us 
// c7: c_us 
// c8: c_us 
// c9: c_us 
// c10: c_us 
// c11: c_us 
// c12: c_us 
// c13: c_us 
// c14: c_us 
// c15: c_us 
// c16: c_us 
// c17: c_us 
// c18: c_us 
// c19: c_us 
// c20: c_us 
// c21: c_us 
// c22: c_us 
// c23: c_us 
// c24: c_us 
// c25: c_us 
// c26: c_us 
// c27: c_us 
// c28: c_us 
// c29: c_us 
// c30: c_us 
// c31: c_us 
// c32: c_us 
// c33: c_us 
// c34: cpol_use 
// c35: cpol_use 
// c36: cpol_use 
// c37: c_us 
// e1: n8881n 
// ema2_l = !(ema2 & data_enable); 
// ema1_l = !(ema1 & data_enable); 
// ema0_l = !(data_enable & ema0); 
// md_dir_l = !(data_enable & brk_dir_l); 
// e2: dec8271 
module m7105b (ac7_l, b_brk_rq, b_last_brk, bdata10, bdata11, bdata8, bdata9, brk_enab_clk, brk_in_clk, btp3_l, btp3_ok, clr_all, clr_all_l, clr_cntrs_l, crc_data, data_in_l, data_state_l, db_cont1_l, db_cont4, device_rk, dsk_rdy_s_r_w_l, dsk_seek_fail_l, file_rdy, idle, idle_l, ld_disk_addrs, n6rk3_ok_l, n6rk4_l, n6rk6, n6rk7, n6rk7_ok, n_t_27x, n_t_31x, n_t_8x, rd_clk1, rd_shft_db_l, sector_addrs_1, shift_crc_l, state_enab_b, strobe, wrt_cmd_l, b_data_state, bdata1, bdata10_l, bdata11_l, bdata7, bk_cycle_l, brk_dir_l, brk_in_prog_l, brk_rq, clr_sector_ad_l, cpma_dis_l, crc16, data0_l, data1_l, data2_l, data3_l, data4_l, data5_l, data6_l, data7_l, data_enab_l, data_enable, drive_status_bad, dsk_cyl_ad128_l, dsk_cyl_ad16_l, dsk_cyl_ad1_l, dsk_cyl_ad2_l, dsk_cyl_ad32_l, dsk_cyl_ad4_l, dsk_cyl_ad64_l, dsk_cyl_ad8_l, dsk_drive0_l, dsk_drive1_l, dsk_drive2_l, dsk_drive3_l, ema0_l, ema1_l, ema2_l, enab_int, enab_seek_done, function00, function01, function02, half_block, hi_data_in, hi_main_shft_l, hi_rd_clk, int_strobe, last_brk, ld_cmd_reg, lo_main_data, lo_main_shft_l, ma0_l, ma10_l, ma11_l, ma1_l, ma2_l, ma3_l, ma4_l, ma5_l, ma6_l, ma7_l, ma8_l, ma9_l, main, main_l, main_pl, mak_l, mams_load_cont_l, md_dir_l, msir_dis_l, n_t_30x, n_t_4x, not_equal_l, priority, rd_brk_l, rdy_s_r_w, rdy_s_r_w_l, seek_fail, shft_surf, tp1, tp4, ts2, ts4, wrt_brk_l, wt_buff_data_l);
input ac7_l;
input b_brk_rq;
input b_last_brk;
input bdata10;
input bdata11;
input bdata8;
input bdata9;
input brk_enab_clk;
input brk_in_clk;
input btp3_l;
input btp3_ok;
input clr_all;
input clr_all_l;
input clr_cntrs_l;
input crc_data;
input data_in_l;
input data_state_l;
input db_cont1_l;
input db_cont4;
input device_rk;
input dsk_rdy_s_r_w_l;
input dsk_seek_fail_l;
input file_rdy;
input idle;
input idle_l;
input ld_disk_addrs;
input n6rk3_ok_l;
input n6rk4_l;
input n6rk6;
input n6rk7;
input n6rk7_ok;
input n_t_27x;
input n_t_31x;
input n_t_8x;
input rd_clk1;
input rd_shft_db_l;
input sector_addrs_1;
input shift_crc_l;
input state_enab_b;
input strobe;
input wrt_cmd_l;
inout b_data_state;
inout bdata1;
inout bdata10_l;
output bdata11_l;
inout bdata7;
output bk_cycle_l;
inout brk_dir_l;
output brk_in_prog_l;
output brk_rq;
output clr_sector_ad_l;
output cpma_dis_l;
inout reg crc16;
input data0_l;
input data1_l;
input data2_l;
input data3_l;
input data4_l;
input data5_l;
input data6_l;
input data7_l;
inout data_enab_l;
inout reg data_enable;
output drive_status_bad;
output dsk_cyl_ad128_l;
output dsk_cyl_ad16_l;
output dsk_cyl_ad1_l;
output dsk_cyl_ad2_l;
output dsk_cyl_ad32_l;
output dsk_cyl_ad4_l;
output dsk_cyl_ad64_l;
output dsk_cyl_ad8_l;
output dsk_drive0_l;
output dsk_drive1_l;
output dsk_drive2_l;
output dsk_drive3_l;
output ema0_l;
output ema1_l;
output ema2_l;
inout reg enab_int;
inout reg enab_seek_done;
inout reg function00;
inout reg function01;
inout reg function02;
inout reg half_block;
output hi_data_in;
inout hi_main_shft_l;
output hi_rd_clk;
input int_strobe;
inout reg last_brk;
inout ld_cmd_reg;
output lo_main_data;
output lo_main_shft_l;
output ma0_l;
output ma10_l;
output ma11_l;
output ma1_l;
output ma2_l;
output ma3_l;
output ma4_l;
output ma5_l;
output ma6_l;
output ma7_l;
output ma8_l;
output ma9_l;
inout reg main;
inout main_l;
inout main_pl;
output mak_l;
output mams_load_cont_l;
output md_dir_l;
output msir_dis_l;
output n_t_30x;
output n_t_4x;
inout not_equal_l;
output priority;
inout rd_brk_l;
inout rdy_s_r_w;
output rdy_s_r_w_l;
output seek_fail;
output shft_surf;
input tp1;
input tp4;
input ts2;
input ts4;
inout wrt_brk_l;
output wt_buff_data_l;

reg brk_dir_m;
reg brk_enable_l_m;
reg brk_in_l_m;
reg crc1_m;
reg crc10_m;
reg crc11_m;
reg crc12_m;
reg crc13_m;
reg crc14_m;
reg crc15_m;
reg crc16_m;
reg crc2_m;
reg crc3_m;
reg crc4_m;
reg crc5_m;
reg crc6_m;
reg crc7_m;
reg crc8_m;
reg crc9_m;
reg data_enable_m;
reg ema0_m;
reg ema1_m;
reg ema2_m;
reg enab_int_m;
reg enab_seek_done_m;
reg ext_cyl_addrs_m;
reg function00_m;
reg function01_m;
reg function02_m;
reg half_block_m;
reg last_brk_m;
reg main_m;
reg mak_m;
reg malc_m;
reg n_t_26x_m;
reg n_t_37x_m;
reg n_t_38x_m;
reg n_t_39x_m;
reg n_t_40x_m;
reg n_t_41x_m;
reg n_t_42x_m;
reg n_t_43x_m;
reg n_t_44x_m;
reg n_t_45x_m;
reg n_t_47x_m;
reg n_t_48x_m;
reg nbr_m;
reg not_equal_m;
reg unit_sel0_m;
reg unit_sel1_m;

reg ema0;
reg ema1;
reg crc9;
reg crc10;
reg crc11;
reg crc12;
reg crc13;
reg n_t_39x;
reg n_t_38x;
reg n_t_37x;
reg n_t_26x;
reg crc4;
reg crc5;
reg crc6;
reg crc7;
reg crc8;
reg ema2;
reg unit_sel0;
reg unit_sel1;
reg ext_cyl_addrs;
reg n_t_47x;
reg n_t_44x;
reg n_t_45x;
reg n_t_42x;
reg n_t_48x;
reg n_t_41x;
reg n_t_43x;
reg n_t_40x;
reg crc1;
reg crc2;
reg crc3;
reg crc14;
reg crc15;
reg malc;
reg not_equal;
reg brk_dir;
reg nbr;
reg mak;
reg brk_enable_l;
reg brk_in_l;
wire bdata0;
wire bdata2;
wire bdata3;
wire bdata4;
wire bdata5;
wire bdata6;
wire btp4;
wire clr_dsk_ad_l;
wire crc_main_data_l;
wire crc_main_shft_l;
wire disk_priority;
wire drive0_l;
wire drive1_l;
wire drive2_l;
wire drive3_l;
wire hi_main_data_l;
wire ld_shft_cmd_reg_l;
wire mad;
wire main_data;
wire main_enab;
wire mux_input;
wire n_t_10x;
wire n_t_11x;
wire n_t_12x;
wire n_t_13x;
wire n_t_14x;
wire n_t_16x;
wire n_t_17x;
wire n_t_18x;
wire n_t_19x;
wire n_t_1x;
wire n_t_20x;
wire n_t_21x;
wire n_t_22x;
wire n_t_23x;
wire n_t_24x;
wire n_t_25x;
wire n_t_29x;
wire n_t_2x;
wire n_t_32x;
wire n_t_33x;
wire n_t_34x;
wire n_t_35x;
wire n_t_3x;
wire n_t_49x;
wire n_t_55x;
wire n_t_5x;
wire n_t_6x;
wire n_t_7x;
wire n_t_9x;
wire set_main_brk_l;
wire shft_cmd_reg;
wire start_clr_l;
always @(ld_shft_cmd_reg_l, clr_all_l, bdata0, n6rk6, n6rk7, function00, n6rk6, n6rk7)
  if (~clr_all_l) begin
    function00_m <= 1'b0;
  end else
  if (~(~ld_shft_cmd_reg_l)) begin
    function00_m <= bdata0 & n6rk6 & ~n6rk7
                       | function00 & ~n6rk6 & ~n6rk7;
  end
always @(ld_shft_cmd_reg_l, clr_all_l, function00_m)
  if (~clr_all_l) begin
    function00 <= 1'b0;
  end else
  if (~ld_shft_cmd_reg_l) begin
    function00 <= function00_m;
  end
always @(ld_shft_cmd_reg_l, clr_all_l, function00, n6rk7, bdata1, n6rk6, n6rk7, function01, n6rk6, n6rk7)
  if (~clr_all_l) begin
    function01_m <= 1'b0;
  end else
  if (~(~ld_shft_cmd_reg_l)) begin
    function01_m <= function00 & n6rk7
                       | bdata1 & n6rk6 & ~n6rk7
                       | function01 & ~n6rk6 & ~n6rk7;
  end
always @(ld_shft_cmd_reg_l, clr_all_l, function01_m)
  if (~clr_all_l) begin
    function01 <= 1'b0;
  end else
  if (~ld_shft_cmd_reg_l) begin
    function01 <= function01_m;
  end
always @(ld_shft_cmd_reg_l, clr_all_l, function01, n6rk7, bdata2, n6rk6, n6rk7, function02, n6rk6, n6rk7)
  if (~clr_all_l) begin
    function02_m <= 1'b0;
  end else
  if (~(~ld_shft_cmd_reg_l)) begin
    function02_m <= function01 & n6rk7
                       | bdata2 & n6rk6 & ~n6rk7
                       | function02 & ~n6rk6 & ~n6rk7;
  end
always @(ld_shft_cmd_reg_l, clr_all_l, function02_m)
  if (~clr_all_l) begin
    function02 <= 1'b0;
  end else
  if (~ld_shft_cmd_reg_l) begin
    function02 <= function02_m;
  end
always @(ld_shft_cmd_reg_l, clr_all_l, function02, n6rk7, bdata3, n6rk6, n6rk7, enab_int, n6rk6, n6rk7)
  if (~clr_all_l) begin
    enab_int_m <= 1'b0;
  end else
  if (~(~ld_shft_cmd_reg_l)) begin
    enab_int_m <= function02 & n6rk7
                     | bdata3 & n6rk6 & ~n6rk7
                     | enab_int & ~n6rk6 & ~n6rk7;
  end
always @(ld_shft_cmd_reg_l, clr_all_l, enab_int_m)
  if (~clr_all_l) begin
    enab_int <= 1'b0;
  end else
  if (~ld_shft_cmd_reg_l) begin
    enab_int <= enab_int_m;
  end
// e3: dec8271 
always @(ld_shft_cmd_reg_l, clr_all_l, enab_int, n6rk7, bdata4, n6rk6, n6rk7, enab_seek_done, n6rk6, n6rk7)
  if (~clr_all_l) begin
    enab_seek_done_m <= 1'b0;
  end else
  if (~(~ld_shft_cmd_reg_l)) begin
    enab_seek_done_m <= enab_int & n6rk7
                           | bdata4 & n6rk6 & ~n6rk7
                           | enab_seek_done & ~n6rk6 & ~n6rk7;
  end
always @(ld_shft_cmd_reg_l, clr_all_l, enab_seek_done_m)
  if (~clr_all_l) begin
    enab_seek_done <= 1'b0;
  end else
  if (~ld_shft_cmd_reg_l) begin
    enab_seek_done <= enab_seek_done_m;
  end
always @(ld_shft_cmd_reg_l, clr_all_l, enab_seek_done, n6rk7, bdata5, n6rk6, n6rk7, half_block, n6rk6, n6rk7)
  if (~clr_all_l) begin
    half_block_m <= 1'b0;
  end else
  if (~(~ld_shft_cmd_reg_l)) begin
    half_block_m <= enab_seek_done & n6rk7
                       | bdata5 & n6rk6 & ~n6rk7
                       | half_block & ~n6rk6 & ~n6rk7;
  end
always @(ld_shft_cmd_reg_l, clr_all_l, half_block_m)
  if (~clr_all_l) begin
    half_block <= 1'b0;
  end else
  if (~ld_shft_cmd_reg_l) begin
    half_block <= half_block_m;
  end
always @(ld_shft_cmd_reg_l, clr_all_l, half_block, n6rk7, bdata6, n6rk6, n6rk7, ema0, n6rk6, n6rk7)
  if (~clr_all_l) begin
    ema0_m <= 1'b0;
  end else
  if (~(~ld_shft_cmd_reg_l)) begin
    ema0_m <= half_block & n6rk7
                 | bdata6 & n6rk6 & ~n6rk7
                 | ema0 & ~n6rk6 & ~n6rk7;
  end
always @(ld_shft_cmd_reg_l, clr_all_l, ema0_m)
  if (~clr_all_l) begin
    ema0 <= 1'b0;
  end else
  if (~ld_shft_cmd_reg_l) begin
    ema0 <= ema0_m;
  end
always @(ld_shft_cmd_reg_l, clr_all_l, ema0, n6rk7, bdata7, n6rk6, n6rk7, ema1, n6rk6, n6rk7)
  if (~clr_all_l) begin
    ema1_m <= 1'b0;
  end else
  if (~(~ld_shft_cmd_reg_l)) begin
    ema1_m <= ema0 & n6rk7
                 | bdata7 & n6rk6 & ~n6rk7
                 | ema1 & ~n6rk6 & ~n6rk7;
  end
always @(ld_shft_cmd_reg_l, clr_all_l, ema1_m)
  if (~clr_all_l) begin
    ema1 <= 1'b0;
  end else
  if (~ld_shft_cmd_reg_l) begin
    ema1 <= ema1_m;
  end
// e4: sn7496 
always @(n_t_2x, ld_disk_addrs, clr_dsk_ad_l, ld_disk_addrs, bdata4, crc8)
  if (~ld_disk_addrs & ~clr_dsk_ad_l) begin
    crc9_m <= 1'b0;
  end else
  if (ld_disk_addrs & bdata4) begin
    crc9_m <= 1'b1;
  end else
  if (~(n_t_2x)) begin
    crc9_m <= crc8;
  end
always @(n_t_2x, ld_disk_addrs, clr_dsk_ad_l, ld_disk_addrs, bdata4, crc9_m)
  if (~ld_disk_addrs & ~clr_dsk_ad_l) begin
    crc9 <= 1'b0;
  end else
  if (ld_disk_addrs & bdata4) begin
    crc9 <= 1'b1;
  end else
  if (n_t_2x) begin
    crc9 <= crc9_m;
  end
always @(n_t_2x, ld_disk_addrs, clr_dsk_ad_l, ld_disk_addrs, bdata5, crc9)
  if (~ld_disk_addrs & ~clr_dsk_ad_l) begin
    crc10_m <= 1'b0;
  end else
  if (ld_disk_addrs & bdata5) begin
    crc10_m <= 1'b1;
  end else
  if (~(n_t_2x)) begin
    crc10_m <= crc9;
  end
always @(n_t_2x, ld_disk_addrs, clr_dsk_ad_l, ld_disk_addrs, bdata5, crc10_m)
  if (~ld_disk_addrs & ~clr_dsk_ad_l) begin
    crc10 <= 1'b0;
  end else
  if (ld_disk_addrs & bdata5) begin
    crc10 <= 1'b1;
  end else
  if (n_t_2x) begin
    crc10 <= crc10_m;
  end
always @(n_t_2x, ld_disk_addrs, clr_dsk_ad_l, ld_disk_addrs, bdata6, crc10)
  if (~ld_disk_addrs & ~clr_dsk_ad_l) begin
    crc11_m <= 1'b0;
  end else
  if (ld_disk_addrs & bdata6) begin
    crc11_m <= 1'b1;
  end else
  if (~(n_t_2x)) begin
    crc11_m <= crc10;
  end
always @(n_t_2x, ld_disk_addrs, clr_dsk_ad_l, ld_disk_addrs, bdata6, crc11_m)
  if (~ld_disk_addrs & ~clr_dsk_ad_l) begin
    crc11 <= 1'b0;
  end else
  if (ld_disk_addrs & bdata6) begin
    crc11 <= 1'b1;
  end else
  if (n_t_2x) begin
    crc11 <= crc11_m;
  end
always @(n_t_2x, ld_disk_addrs, clr_dsk_ad_l, crc11)
  if (~ld_disk_addrs & ~clr_dsk_ad_l) begin
    crc12_m <= 1'b0;
  end else
  if (~(n_t_2x)) begin
    crc12_m <= crc11;
  end
always @(n_t_2x, ld_disk_addrs, clr_dsk_ad_l, crc12_m)
  if (~ld_disk_addrs & ~clr_dsk_ad_l) begin
    crc12 <= 1'b0;
  end else
  if (n_t_2x) begin
    crc12 <= crc12_m;
  end
always @(n_t_2x, ld_disk_addrs, clr_dsk_ad_l, crc12)
  if (~ld_disk_addrs & ~clr_dsk_ad_l) begin
    crc13_m <= 1'b0;
  end else
  if (~(n_t_2x)) begin
    crc13_m <= crc12;
  end
always @(n_t_2x, ld_disk_addrs, clr_dsk_ad_l, crc13_m)
  if (~ld_disk_addrs & ~clr_dsk_ad_l) begin
    crc13 <= 1'b0;
  end else
  if (n_t_2x) begin
    crc13 <= crc13_m;
  end
// e5: ds75452n 
// dsk_cyl_ad1_l = !(!(crc11 & strobe)); 
// dsk_cyl_ad8_l = !(!(crc8 & strobe)); 
// e6: ds75452n 
// dsk_cyl_ad4_l = !(!(strobe & crc9)); 
// dsk_cyl_ad2_l = !(!(crc10 & strobe)); 
// e7: n8881n 
// ma3_l = !(n_t_39x & mak); 
// ma2_l = !(n_t_38x & mak); 
// ma1_l = !(mak & n_t_37x); 
// ma0_l = !(mak & n_t_26x); 
// e8: sn74161 
always @(n_t_29x, clr_all_l, bdata3, n6rk4_l, n_t_19x, n6rk4_l, bdata3, n6rk4_l, n_t_19x, n6rk4_l, n_t_39x)
  if (~clr_all_l) begin
    n_t_39x_m <= 1'b0;
  end else
  if (~(~n_t_29x)) begin
    n_t_39x_m <= ~(~bdata3 & ~n6rk4_l) & (n_t_19x
                                             | ~n6rk4_l)? (~(bdata3 & ~n6rk4_l) & (n_t_19x
                                            | ~n6rk4_l)? ~n_t_39x: 1'b1) : (~(bdata3 & ~n6rk4_l) & (n_t_19x
                                            | ~n6rk4_l)? 1'b0: n_t_39x);
  end
always @(n_t_29x, clr_all_l, n_t_39x_m)
  if (~clr_all_l) begin
    n_t_39x <= 1'b0;
  end else
  if (~n_t_29x) begin
    n_t_39x <= n_t_39x_m;
  end
always @(n_t_29x, clr_all_l, bdata2, n6rk4_l, n_t_19x, n_t_39x, n6rk4_l, bdata2, n6rk4_l, n_t_19x, n_t_39x, n6rk4_l, n_t_38x)
  if (~clr_all_l) begin
    n_t_38x_m <= 1'b0;
  end else
  if (~(~n_t_29x)) begin
    n_t_38x_m <= ~(~bdata2 & ~n6rk4_l) & ((n_t_19x & n_t_39x)
                                             | ~n6rk4_l)? (~(bdata2 & ~n6rk4_l) & ((n_t_19x & n_t_39x)
                                            | ~n6rk4_l)? ~n_t_38x: 1'b1) : (~(bdata2 & ~n6rk4_l) & ((n_t_19x & n_t_39x)
                                            | ~n6rk4_l)? 1'b0: n_t_38x);
  end
always @(n_t_29x, clr_all_l, n_t_38x_m)
  if (~clr_all_l) begin
    n_t_38x <= 1'b0;
  end else
  if (~n_t_29x) begin
    n_t_38x <= n_t_38x_m;
  end
always @(n_t_29x, clr_all_l, bdata1, n6rk4_l, n_t_19x, n_t_39x, n_t_38x, n6rk4_l, bdata1, n6rk4_l, n_t_19x, n_t_39x, n_t_38x, n6rk4_l, n_t_37x)
  if (~clr_all_l) begin
    n_t_37x_m <= 1'b0;
  end else
  if (~(~n_t_29x)) begin
    n_t_37x_m <= ~(~bdata1 & ~n6rk4_l) & ((n_t_19x & n_t_39x & n_t_38x)
                                             | ~n6rk4_l)? (~(bdata1 & ~n6rk4_l) & ((n_t_19x & n_t_39x & n_t_38x)
                                            | ~n6rk4_l)? ~n_t_37x: 1'b1) : (~(bdata1 & ~n6rk4_l) & ((n_t_19x & n_t_39x & n_t_38x)
                                            | ~n6rk4_l)? 1'b0: n_t_37x);
  end
always @(n_t_29x, clr_all_l, n_t_37x_m)
  if (~clr_all_l) begin
    n_t_37x <= 1'b0;
  end else
  if (~n_t_29x) begin
    n_t_37x <= n_t_37x_m;
  end
always @(n_t_29x, clr_all_l, bdata0, n6rk4_l, n_t_19x, n_t_39x, n_t_38x, n_t_37x, n6rk4_l, bdata0, n6rk4_l, n_t_19x, n_t_39x, n_t_38x, n_t_37x, n6rk4_l, n_t_26x)
  if (~clr_all_l) begin
    n_t_26x_m <= 1'b0;
  end else
  if (~(~n_t_29x)) begin
    n_t_26x_m <= ~(~bdata0 & ~n6rk4_l) & ((n_t_19x & n_t_39x & n_t_38x & n_t_37x)
                                             | ~n6rk4_l)? (~(bdata0 & ~n6rk4_l) & ((n_t_19x & n_t_39x & n_t_38x & n_t_37x)
                                            | ~n6rk4_l)? ~n_t_26x: 1'b1) : (~(bdata0 & ~n6rk4_l) & ((n_t_19x & n_t_39x & n_t_38x & n_t_37x)
                                            | ~n6rk4_l)? 1'b0: n_t_26x);
  end
always @(n_t_29x, clr_all_l, n_t_26x_m)
  if (~clr_all_l) begin
    n_t_26x <= 1'b0;
  end else
  if (~n_t_29x) begin
    n_t_26x <= n_t_26x_m;
  end
// e9: sn7452 
assign n_t_1x = ext_cyl_addrs & bdata3
                 | bdata4 & sector_addrs_1
                 | bdata2 & crc16;
// e10: sn74155 
assign drive0_l = ~(~unit_sel0 & ~unit_sel1 & ~ld_cmd_reg);
assign drive1_l = ~(~unit_sel0 & unit_sel1 & ~ld_cmd_reg);
assign drive2_l = ~(unit_sel0 & ~unit_sel1 & ~ld_cmd_reg);
assign drive3_l = ~(unit_sel0 & unit_sel1 & ~ld_cmd_reg);
// e11: ds75451n 
// dsk_drive1_l = !drive1_l; 
// dsk_drive0_l = !drive0_l; 
// e12: ds75451n 
// dsk_drive3_l = !drive3_l; 
// dsk_drive2_l = !drive2_l; 
// e13: sp380n 
assign bdata3 = ~(data_enab_l
                   | data3_l);
assign bdata2 = ~(data2_l
                   | data_enab_l);
assign bdata0 = ~(data_enab_l
                   | data0_l);
assign bdata1 = ~(data_enab_l
                   | data1_l);
// e14: sn7496 
always @(n_t_2x, ld_disk_addrs, clr_dsk_ad_l, ld_disk_addrs, ext_cyl_addrs, crc3)
  if (~ld_disk_addrs & ~clr_dsk_ad_l) begin
    crc4_m <= 1'b0;
  end else
  if (ld_disk_addrs & ext_cyl_addrs) begin
    crc4_m <= 1'b1;
  end else
  if (~(n_t_2x)) begin
    crc4_m <= crc3;
  end
always @(n_t_2x, ld_disk_addrs, clr_dsk_ad_l, ld_disk_addrs, ext_cyl_addrs, crc4_m)
  if (~ld_disk_addrs & ~clr_dsk_ad_l) begin
    crc4 <= 1'b0;
  end else
  if (ld_disk_addrs & ext_cyl_addrs) begin
    crc4 <= 1'b1;
  end else
  if (n_t_2x) begin
    crc4 <= crc4_m;
  end
always @(n_t_2x, ld_disk_addrs, clr_dsk_ad_l, ld_disk_addrs, bdata0, crc4)
  if (~ld_disk_addrs & ~clr_dsk_ad_l) begin
    crc5_m <= 1'b0;
  end else
  if (ld_disk_addrs & bdata0) begin
    crc5_m <= 1'b1;
  end else
  if (~(n_t_2x)) begin
    crc5_m <= crc4;
  end
always @(n_t_2x, ld_disk_addrs, clr_dsk_ad_l, ld_disk_addrs, bdata0, crc5_m)
  if (~ld_disk_addrs & ~clr_dsk_ad_l) begin
    crc5 <= 1'b0;
  end else
  if (ld_disk_addrs & bdata0) begin
    crc5 <= 1'b1;
  end else
  if (n_t_2x) begin
    crc5 <= crc5_m;
  end
always @(n_t_2x, ld_disk_addrs, clr_dsk_ad_l, ld_disk_addrs, bdata1, crc5)
  if (~ld_disk_addrs & ~clr_dsk_ad_l) begin
    crc6_m <= 1'b0;
  end else
  if (ld_disk_addrs & bdata1) begin
    crc6_m <= 1'b1;
  end else
  if (~(n_t_2x)) begin
    crc6_m <= crc5;
  end
always @(n_t_2x, ld_disk_addrs, clr_dsk_ad_l, ld_disk_addrs, bdata1, crc6_m)
  if (~ld_disk_addrs & ~clr_dsk_ad_l) begin
    crc6 <= 1'b0;
  end else
  if (ld_disk_addrs & bdata1) begin
    crc6 <= 1'b1;
  end else
  if (n_t_2x) begin
    crc6 <= crc6_m;
  end
always @(n_t_2x, ld_disk_addrs, clr_dsk_ad_l, ld_disk_addrs, bdata2, crc6)
  if (~ld_disk_addrs & ~clr_dsk_ad_l) begin
    crc7_m <= 1'b0;
  end else
  if (ld_disk_addrs & bdata2) begin
    crc7_m <= 1'b1;
  end else
  if (~(n_t_2x)) begin
    crc7_m <= crc6;
  end
always @(n_t_2x, ld_disk_addrs, clr_dsk_ad_l, ld_disk_addrs, bdata2, crc7_m)
  if (~ld_disk_addrs & ~clr_dsk_ad_l) begin
    crc7 <= 1'b0;
  end else
  if (ld_disk_addrs & bdata2) begin
    crc7 <= 1'b1;
  end else
  if (n_t_2x) begin
    crc7 <= crc7_m;
  end
always @(n_t_2x, ld_disk_addrs, clr_dsk_ad_l, ld_disk_addrs, bdata3, crc7)
  if (~ld_disk_addrs & ~clr_dsk_ad_l) begin
    crc8_m <= 1'b0;
  end else
  if (ld_disk_addrs & bdata3) begin
    crc8_m <= 1'b1;
  end else
  if (~(n_t_2x)) begin
    crc8_m <= crc7;
  end
always @(n_t_2x, ld_disk_addrs, clr_dsk_ad_l, ld_disk_addrs, bdata3, crc8_m)
  if (~ld_disk_addrs & ~clr_dsk_ad_l) begin
    crc8 <= 1'b0;
  end else
  if (ld_disk_addrs & bdata3) begin
    crc8 <= 1'b1;
  end else
  if (n_t_2x) begin
    crc8 <= crc8_m;
  end
// e15: ds75452n 
// dsk_cyl_ad16_l = !(!(strobe & crc7)); 
// dsk_cyl_ad32_l = !(!(strobe & crc6)); 
// e16: ds75452n 
// dsk_cyl_ad128_l = !(!(strobe & crc4)); 
// dsk_cyl_ad64_l = !(!(crc5 & strobe)); 
// e17: dec8271 
always @(ld_shft_cmd_reg_l, clr_all_l, ema1, n6rk7, bdata8, n6rk6, n6rk7, ema2, n6rk6, n6rk7)
  if (~clr_all_l) begin
    ema2_m <= 1'b0;
  end else
  if (~(~ld_shft_cmd_reg_l)) begin
    ema2_m <= ema1 & n6rk7
                 | bdata8 & n6rk6 & ~n6rk7
                 | ema2 & ~n6rk6 & ~n6rk7;
  end
always @(ld_shft_cmd_reg_l, clr_all_l, ema2_m)
  if (~clr_all_l) begin
    ema2 <= 1'b0;
  end else
  if (~ld_shft_cmd_reg_l) begin
    ema2 <= ema2_m;
  end
always @(ld_shft_cmd_reg_l, clr_all_l, ema2, n6rk7, bdata9, n6rk6, n6rk7, unit_sel0, n6rk6, n6rk7)
  if (~clr_all_l) begin
    unit_sel0_m <= 1'b0;
  end else
  if (~(~ld_shft_cmd_reg_l)) begin
    unit_sel0_m <= ema2 & n6rk7
                      | bdata9 & n6rk6 & ~n6rk7
                      | unit_sel0 & ~n6rk6 & ~n6rk7;
  end
always @(ld_shft_cmd_reg_l, clr_all_l, unit_sel0_m)
  if (~clr_all_l) begin
    unit_sel0 <= 1'b0;
  end else
  if (~ld_shft_cmd_reg_l) begin
    unit_sel0 <= unit_sel0_m;
  end
always @(ld_shft_cmd_reg_l, clr_all_l, unit_sel0, n6rk7, bdata10, n6rk6, n6rk7, unit_sel1, n6rk6, n6rk7)
  if (~clr_all_l) begin
    unit_sel1_m <= 1'b0;
  end else
  if (~(~ld_shft_cmd_reg_l)) begin
    unit_sel1_m <= unit_sel0 & n6rk7
                      | bdata10 & n6rk6 & ~n6rk7
                      | unit_sel1 & ~n6rk6 & ~n6rk7;
  end
always @(ld_shft_cmd_reg_l, clr_all_l, unit_sel1_m)
  if (~clr_all_l) begin
    unit_sel1 <= 1'b0;
  end else
  if (~ld_shft_cmd_reg_l) begin
    unit_sel1 <= unit_sel1_m;
  end
always @(ld_shft_cmd_reg_l, clr_all_l, unit_sel1, n6rk7, bdata11, n6rk6, n6rk7, ext_cyl_addrs, n6rk6, n6rk7)
  if (~clr_all_l) begin
    ext_cyl_addrs_m <= 1'b0;
  end else
  if (~(~ld_shft_cmd_reg_l)) begin
    ext_cyl_addrs_m <= unit_sel1 & n6rk7
                          | bdata11 & n6rk6 & ~n6rk7
                          | ext_cyl_addrs & ~n6rk6 & ~n6rk7;
  end
always @(ld_shft_cmd_reg_l, clr_all_l, ext_cyl_addrs_m)
  if (~clr_all_l) begin
    ext_cyl_addrs <= 1'b0;
  end else
  if (~ld_shft_cmd_reg_l) begin
    ext_cyl_addrs <= ext_cyl_addrs_m;
  end
// e18: sn74161 
always @(n_t_29x, clr_all_l, bdata11, n6rk4_l, bdata11, n6rk4_l, n_t_47x)
  if (~clr_all_l) begin
    n_t_47x_m <= 1'b0;
  end else
  if (~(~n_t_29x)) begin
    n_t_47x_m <= ~(~bdata11 & ~n6rk4_l)? (~(bdata11 & ~n6rk4_l)? ~n_t_47x: 1'b1) : (~(bdata11 & ~n6rk4_l)? 1'b0: n_t_47x);
  end
always @(n_t_29x, clr_all_l, n_t_47x_m)
  if (~clr_all_l) begin
    n_t_47x <= 1'b0;
  end else
  if (~n_t_29x) begin
    n_t_47x <= n_t_47x_m;
  end
always @(n_t_29x, clr_all_l, bdata10, n6rk4_l, n_t_47x, n6rk4_l, bdata10, n6rk4_l, n_t_47x, n6rk4_l, n_t_44x)
  if (~clr_all_l) begin
    n_t_44x_m <= 1'b0;
  end else
  if (~(~n_t_29x)) begin
    n_t_44x_m <= ~(~bdata10 & ~n6rk4_l) & (n_t_47x
                                              | ~n6rk4_l)? (~(bdata10 & ~n6rk4_l) & (n_t_47x
                                             | ~n6rk4_l)? ~n_t_44x: 1'b1) : (~(bdata10 & ~n6rk4_l) & (n_t_47x
                                             | ~n6rk4_l)? 1'b0: n_t_44x);
  end
always @(n_t_29x, clr_all_l, n_t_44x_m)
  if (~clr_all_l) begin
    n_t_44x <= 1'b0;
  end else
  if (~n_t_29x) begin
    n_t_44x <= n_t_44x_m;
  end
always @(n_t_29x, clr_all_l, bdata9, n6rk4_l, n_t_47x, n_t_44x, n6rk4_l, bdata9, n6rk4_l, n_t_47x, n_t_44x, n6rk4_l, n_t_45x)
  if (~clr_all_l) begin
    n_t_45x_m <= 1'b0;
  end else
  if (~(~n_t_29x)) begin
    n_t_45x_m <= ~(~bdata9 & ~n6rk4_l) & ((n_t_47x & n_t_44x)
                                             | ~n6rk4_l)? (~(bdata9 & ~n6rk4_l) & ((n_t_47x & n_t_44x)
                                            | ~n6rk4_l)? ~n_t_45x: 1'b1) : (~(bdata9 & ~n6rk4_l) & ((n_t_47x & n_t_44x)
                                            | ~n6rk4_l)? 1'b0: n_t_45x);
  end
always @(n_t_29x, clr_all_l, n_t_45x_m)
  if (~clr_all_l) begin
    n_t_45x <= 1'b0;
  end else
  if (~n_t_29x) begin
    n_t_45x <= n_t_45x_m;
  end
always @(n_t_29x, clr_all_l, bdata8, n6rk4_l, n_t_47x, n_t_44x, n_t_45x, n6rk4_l, bdata8, n6rk4_l, n_t_47x, n_t_44x, n_t_45x, n6rk4_l, n_t_42x)
  if (~clr_all_l) begin
    n_t_42x_m <= 1'b0;
  end else
  if (~(~n_t_29x)) begin
    n_t_42x_m <= ~(~bdata8 & ~n6rk4_l) & ((n_t_47x & n_t_44x & n_t_45x)
                                             | ~n6rk4_l)? (~(bdata8 & ~n6rk4_l) & ((n_t_47x & n_t_44x & n_t_45x)
                                            | ~n6rk4_l)? ~n_t_42x: 1'b1) : (~(bdata8 & ~n6rk4_l) & ((n_t_47x & n_t_44x & n_t_45x)
                                            | ~n6rk4_l)? 1'b0: n_t_42x);
  end
always @(n_t_29x, clr_all_l, n_t_42x_m)
  if (~clr_all_l) begin
    n_t_42x <= 1'b0;
  end else
  if (~n_t_29x) begin
    n_t_42x <= n_t_42x_m;
  end
assign n_t_18x = n_t_42x & n_t_45x & n_t_44x & n_t_47x;
// e19: sn74h00 
assign clr_sector_ad_l = ~(n_t_9x & idle);
assign drive_status_bad = ~(file_rdy & rdy_s_r_w);
// e20: n8881n 
// ma7_l = !(mak & n_t_48x); 
// ma6_l = !(n_t_41x & mak); 
// ma4_l = !(mak & n_t_40x); 
// ma5_l = !(mak & n_t_43x); 
// e21: sn74161 
always @(n_t_29x, clr_all_l, bdata7, n6rk4_l, n_t_18x, n6rk4_l, bdata7, n6rk4_l, n_t_18x, n6rk4_l, n_t_48x)
  if (~clr_all_l) begin
    n_t_48x_m <= 1'b0;
  end else
  if (~(~n_t_29x)) begin
    n_t_48x_m <= ~(~bdata7 & ~n6rk4_l) & (n_t_18x
                                             | ~n6rk4_l)? (~(bdata7 & ~n6rk4_l) & (n_t_18x
                                            | ~n6rk4_l)? ~n_t_48x: 1'b1) : (~(bdata7 & ~n6rk4_l) & (n_t_18x
                                            | ~n6rk4_l)? 1'b0: n_t_48x);
  end
always @(n_t_29x, clr_all_l, n_t_48x_m)
  if (~clr_all_l) begin
    n_t_48x <= 1'b0;
  end else
  if (~n_t_29x) begin
    n_t_48x <= n_t_48x_m;
  end
always @(n_t_29x, clr_all_l, bdata6, n6rk4_l, n_t_18x, n_t_48x, n6rk4_l, bdata6, n6rk4_l, n_t_18x, n_t_48x, n6rk4_l, n_t_41x)
  if (~clr_all_l) begin
    n_t_41x_m <= 1'b0;
  end else
  if (~(~n_t_29x)) begin
    n_t_41x_m <= ~(~bdata6 & ~n6rk4_l) & ((n_t_18x & n_t_48x)
                                             | ~n6rk4_l)? (~(bdata6 & ~n6rk4_l) & ((n_t_18x & n_t_48x)
                                            | ~n6rk4_l)? ~n_t_41x: 1'b1) : (~(bdata6 & ~n6rk4_l) & ((n_t_18x & n_t_48x)
                                            | ~n6rk4_l)? 1'b0: n_t_41x);
  end
always @(n_t_29x, clr_all_l, n_t_41x_m)
  if (~clr_all_l) begin
    n_t_41x <= 1'b0;
  end else
  if (~n_t_29x) begin
    n_t_41x <= n_t_41x_m;
  end
always @(n_t_29x, clr_all_l, bdata5, n6rk4_l, n_t_18x, n_t_48x, n_t_41x, n6rk4_l, bdata5, n6rk4_l, n_t_18x, n_t_48x, n_t_41x, n6rk4_l, n_t_43x)
  if (~clr_all_l) begin
    n_t_43x_m <= 1'b0;
  end else
  if (~(~n_t_29x)) begin
    n_t_43x_m <= ~(~bdata5 & ~n6rk4_l) & ((n_t_18x & n_t_48x & n_t_41x)
                                             | ~n6rk4_l)? (~(bdata5 & ~n6rk4_l) & ((n_t_18x & n_t_48x & n_t_41x)
                                            | ~n6rk4_l)? ~n_t_43x: 1'b1) : (~(bdata5 & ~n6rk4_l) & ((n_t_18x & n_t_48x & n_t_41x)
                                            | ~n6rk4_l)? 1'b0: n_t_43x);
  end
always @(n_t_29x, clr_all_l, n_t_43x_m)
  if (~clr_all_l) begin
    n_t_43x <= 1'b0;
  end else
  if (~n_t_29x) begin
    n_t_43x <= n_t_43x_m;
  end
always @(n_t_29x, clr_all_l, bdata4, n6rk4_l, n_t_18x, n_t_48x, n_t_41x, n_t_43x, n6rk4_l, bdata4, n6rk4_l, n_t_18x, n_t_48x, n_t_41x, n_t_43x, n6rk4_l, n_t_40x)
  if (~clr_all_l) begin
    n_t_40x_m <= 1'b0;
  end else
  if (~(~n_t_29x)) begin
    n_t_40x_m <= ~(~bdata4 & ~n6rk4_l) & ((n_t_18x & n_t_48x & n_t_41x & n_t_43x)
                                             | ~n6rk4_l)? (~(bdata4 & ~n6rk4_l) & ((n_t_18x & n_t_48x & n_t_41x & n_t_43x)
                                            | ~n6rk4_l)? ~n_t_40x: 1'b1) : (~(bdata4 & ~n6rk4_l) & ((n_t_18x & n_t_48x & n_t_41x & n_t_43x)
                                            | ~n6rk4_l)? 1'b0: n_t_40x);
  end
always @(n_t_29x, clr_all_l, n_t_40x_m)
  if (~clr_all_l) begin
    n_t_40x <= 1'b0;
  end else
  if (~n_t_29x) begin
    n_t_40x <= n_t_40x_m;
  end
assign n_t_19x = n_t_18x & n_t_40x & n_t_43x & n_t_41x & n_t_48x;
// e22: sp380n 
assign bdata6 = ~(data6_l
                   | data_enab_l);
assign bdata7 = ~(data_enab_l
                   | data7_l);
assign bdata5 = ~(data5_l
                   | data_enab_l);
assign bdata4 = ~(data_enab_l
                   | data4_l);
// e23: sn74174 
always @(n_t_2x, clr_dsk_ad_l, n_t_21x)
  if (~clr_dsk_ad_l) begin
    crc1_m <= 1'b0;
  end else
  if (~(n_t_2x)) begin
    crc1_m <= n_t_21x;
  end
always @(n_t_2x, clr_dsk_ad_l, crc1_m)
  if (~clr_dsk_ad_l) begin
    crc1 <= 1'b0;
  end else
  if (n_t_2x) begin
    crc1 <= crc1_m;
  end
always @(n_t_2x, clr_dsk_ad_l, crc1)
  if (~clr_dsk_ad_l) begin
    crc2_m <= 1'b0;
  end else
  if (~(n_t_2x)) begin
    crc2_m <= crc1;
  end
always @(n_t_2x, clr_dsk_ad_l, crc2_m)
  if (~clr_dsk_ad_l) begin
    crc2 <= 1'b0;
  end else
  if (n_t_2x) begin
    crc2 <= crc2_m;
  end
always @(n_t_2x, clr_dsk_ad_l, n_t_20x)
  if (~clr_dsk_ad_l) begin
    crc3_m <= 1'b0;
  end else
  if (~(n_t_2x)) begin
    crc3_m <= n_t_20x;
  end
always @(n_t_2x, clr_dsk_ad_l, crc3_m)
  if (~clr_dsk_ad_l) begin
    crc3 <= 1'b0;
  end else
  if (n_t_2x) begin
    crc3 <= crc3_m;
  end
always @(n_t_2x, clr_dsk_ad_l, crc13)
  if (~clr_dsk_ad_l) begin
    crc14_m <= 1'b0;
  end else
  if (~(n_t_2x)) begin
    crc14_m <= crc13;
  end
always @(n_t_2x, clr_dsk_ad_l, crc14_m)
  if (~clr_dsk_ad_l) begin
    crc14 <= 1'b0;
  end else
  if (n_t_2x) begin
    crc14 <= crc14_m;
  end
always @(n_t_2x, clr_dsk_ad_l, crc14)
  if (~clr_dsk_ad_l) begin
    crc15_m <= 1'b0;
  end else
  if (~(n_t_2x)) begin
    crc15_m <= crc14;
  end
always @(n_t_2x, clr_dsk_ad_l, crc15_m)
  if (~clr_dsk_ad_l) begin
    crc15 <= 1'b0;
  end else
  if (n_t_2x) begin
    crc15 <= crc15_m;
  end
always @(n_t_2x, clr_dsk_ad_l, n_t_17x)
  if (~clr_dsk_ad_l) begin
    crc16_m <= 1'b0;
  end else
  if (~(n_t_2x)) begin
    crc16_m <= n_t_17x;
  end
always @(n_t_2x, clr_dsk_ad_l, crc16_m)
  if (~clr_dsk_ad_l) begin
    crc16 <= 1'b0;
  end else
  if (n_t_2x) begin
    crc16 <= crc16_m;
  end
// e24: sn7486 
assign n_t_9x = ~clr_dsk_ad_l;
assign n_t_20x = n_t_10x
                  ^ crc2;
assign n_t_6x = crc_data
                 ^ crc16;
assign n_t_17x = crc15
                  ^ n_t_12x;
// e25: sn7408 
assign n_t_13x = (clr_cntrs_l & start_clr_l);
assign main_pl = (main_enab & n6rk7_ok);
assign n_t_14x = (rd_clk1 & state_enab_b);
assign shft_surf = (main_pl & bdata4);
// e26: n8881n 
// bk_cycle_l = !data_enable; 
// msir_dis_l = !data_enable; 
// brk_in_prog_l = !nbr; 
// mams_load_cont_l = !malc; 
// e27: sp384n 
// e28: sn7402 
assign n_t_49x = ~(clr_all
                    | tp1);
assign n_t_22x = ~(n_t_24x
                    | btp4);
assign start_clr_l = ~(ld_disk_addrs
                        | clr_all);
assign n_t_29x = ~(n_t_22x
                    | n_t_23x);
// e29: sn7400 
assign n_t_5x = ~(b_data_state & n_t_6x);
assign n_t_3x = ~(data_state_l & mux_input);
assign n_t_21x = ~(n_t_3x & n_t_5x);
assign clr_dsk_ad_l = ~(n_t_7x & n_t_8x);
// e30: sn7408 
assign n_t_10x = (b_data_state & n_t_6x);
assign main_enab = (ac7_l & main);
assign lo_main_data = (n_t_1x & main);
assign n_t_12x = (n_t_6x & b_data_state);
// e31: sn7400 
assign n_t_16x = ~(n_t_11x & ~bdata2);
assign lo_main_shft_l = ~(main_pl & n_t_16x);
assign n_t_2x = ~(shift_crc_l & crc_main_shft_l);
assign mux_input = ~(crc_main_data_l & data_in_l);
// e32: sp380n 
assign rdy_s_r_w = ~dsk_rdy_s_r_w_l;
assign n_t_30x = ~n_t_31x;
// e33: sn74h11 
assign mad = disk_priority & nbr;
assign btp4 = tp4;
assign n_t_55x = btp4 & n_t_34x;
// e34: sn74h74 
always @(tp1, clr_all_l, data_enable)
  if (~clr_all_l) begin
    malc_m <= 1'b0;
  end else
  if (~(tp1)) begin
    malc_m <= data_enable;
  end
always @(tp1, clr_all_l, malc_m)
  if (~clr_all_l) begin
    malc <= 1'b0;
  end else
  if (tp1) begin
    malc <= malc_m;
  end
always @(n_t_14x, n_t_13x, not_equal_l, n_t_6x)
  if (~n_t_13x) begin
    not_equal_m <= 1'b0;
  end else
  if (~not_equal_l) begin
    not_equal_m <= 1'b1;
  end else
  if (~(n_t_14x)) begin
    not_equal_m <= n_t_6x;
  end
always @(n_t_14x, n_t_13x, not_equal_l, not_equal_m)
  if (~n_t_13x) begin
    not_equal <= 1'b0;
  end else
  if (~not_equal_l) begin
    not_equal <= 1'b1;
  end else
  if (n_t_14x) begin
    not_equal <= not_equal_m;
  end
assign not_equal_l = ~not_equal;
// e35: sn7474 
always @(tp1, clr_all_l, brk_in_l)
  if (~clr_all_l) begin
    brk_dir_m <= 1'b0;
  end else
  if (~(tp1)) begin
    brk_dir_m <= ~brk_in_l;
  end
always @(tp1, clr_all_l, brk_dir_m)
  if (~clr_all_l) begin
    brk_dir <= 1'b0;
  end else
  if (tp1) begin
    brk_dir <= brk_dir_m;
  end
assign brk_dir_l = ~brk_dir;
always @(int_strobe, n_t_49x, b_brk_rq)
  if (~n_t_49x) begin
    nbr_m <= 1'b0;
  end else
  if (~(int_strobe)) begin
    nbr_m <= b_brk_rq;
  end
always @(int_strobe, n_t_49x, nbr_m)
  if (~n_t_49x) begin
    nbr <= 1'b0;
  end else
  if (int_strobe) begin
    nbr <= nbr_m;
  end
// e36: sn7400 
assign n_t_34x = ~(~data_enable & ~nbr);
assign brk_rq = ~(wrt_brk_l & rd_brk_l);
assign n_t_32x = ~(~set_main_brk_l & wrt_cmd_l);
assign set_main_brk_l = ~(main_pl & bdata6);
// e37: sn74h10 
assign hi_main_shft_l = ~(bdata5 & main_enab & n6rk7_ok);
assign rd_brk_l = ~(db_cont4 & ~brk_enable_l & ~brk_in_l);
assign wt_buff_data_l = ~(data_enable & brk_dir & ~ts2);
// e38: n8881n 
// data_enab_l = !device_rk; 
// cpma_dis_l = !nbr; 
// priority = !(nbr & !ts4); 
// e39: sn74h74 
always @(n6rk7_ok, clr_all_l, main_l, bdata0)
  if (~clr_all_l) begin
    main_m <= 1'b0;
  end else
  if (~main_l) begin
    main_m <= 1'b1;
  end else
  if (~(n6rk7_ok)) begin
    main_m <= bdata0;
  end
always @(n6rk7_ok, clr_all_l, main_l, main_m)
  if (~clr_all_l) begin
    main <= 1'b0;
  end else
  if (~main_l) begin
    main <= 1'b1;
  end else
  if (n6rk7_ok) begin
    main <= main_m;
  end
assign main_l = ~main;
always @(n_t_55x, clr_all_l, mad)
  if (~clr_all_l) begin
    data_enable_m <= 1'b0;
  end else
  if (~(n_t_55x)) begin
    data_enable_m <= mad;
  end
always @(n_t_55x, clr_all_l, data_enable_m)
  if (~clr_all_l) begin
    data_enable <= 1'b0;
  end else
  if (n_t_55x) begin
    data_enable <= data_enable_m;
  end
// e40: sn7400 
assign crc_main_data_l = ~(main_data & bdata2);
assign crc_main_shft_l = ~(bdata2 & main_pl);
assign n_t_35x = ~(mak & main);
assign n_t_24x = ~(~ts4 & data_enable);
// e41: sn7408 
assign shft_cmd_reg = (main_pl & bdata3);
assign ld_cmd_reg = (btp3_ok & n6rk6);
assign n_t_23x = (n_t_25x & btp3_l);
assign n_t_33x = (n_t_35x & start_clr_l);
// e42: sn7404 
assign seek_fail = ~dsk_seek_fail_l;
assign disk_priority = ~n_t_27x;
assign b_data_state = ~data_state_l;
// e43: sn7404 
assign n_t_4x = ~n_t_7x;
assign rdy_s_r_w_l = ~rdy_s_r_w;
assign bdata11_l = ~bdata11;
assign bdata10_l = ~bdata10;
// e44: n8881n 
// ma10_l = !(n_t_44x & mak); 
// ma9_l = !(n_t_45x & mak); 
// ma8_l = !(n_t_42x & mak); 
// ma11_l = !(mak & n_t_47x); 
// e45: sn74h74 
always @(n_t_55x, clr_all_l, mad)
  if (~clr_all_l) begin
    mak_m <= 1'b0;
  end else
  if (~(n_t_55x)) begin
    mak_m <= mad;
  end
always @(n_t_55x, clr_all_l, mak_m)
  if (~clr_all_l) begin
    mak <= 1'b0;
  end else
  if (n_t_55x) begin
    mak <= mak_m;
  end
assign mak_l = ~mak;
always @(b_last_brk, start_clr_l, 1'b1)
  if (~start_clr_l) begin
    last_brk_m <= 1'b0;
  end else
  if (~(~b_last_brk)) begin
    last_brk_m <= 1'b1;
  end
always @(b_last_brk, start_clr_l, last_brk_m)
  if (~start_clr_l) begin
    last_brk <= 1'b0;
  end else
  if (~b_last_brk) begin
    last_brk <= last_brk_m;
  end
// e46: sn7440 
assign wrt_brk_l = ~(~last_brk & ~brk_enable_l & brk_in_l & db_cont1_l);
// e47: sn7402 
assign n_t_11x = ~(bdata3
                    | bdata4);
assign ld_shft_cmd_reg_l = ~(shft_cmd_reg
                              | ld_cmd_reg);
assign main_data = ~(bdata10_l
                      | main_l);
assign n_t_25x = ~(n6rk4_l
                    | idle_l);
// e48: sn74h74 
always @(brk_enab_clk, set_main_brk_l, n_t_33x, 1'b0)
  if (~set_main_brk_l) begin
    brk_enable_l_m <= 1'b0;
  end else
  if (~n_t_33x) begin
    brk_enable_l_m <= 1'b1;
  end else
  if (~(brk_enab_clk)) begin
    brk_enable_l_m <= 1'b0;
  end
always @(brk_enab_clk, set_main_brk_l, n_t_33x, brk_enable_l_m)
  if (~set_main_brk_l) begin
    brk_enable_l <= 1'b0;
  end else
  if (~n_t_33x) begin
    brk_enable_l <= 1'b1;
  end else
  if (brk_enab_clk) begin
    brk_enable_l <= brk_enable_l_m;
  end
always @(brk_in_clk, n_t_32x, start_clr_l, 1'b0)
  if (~n_t_32x) begin
    brk_in_l_m <= 1'b0;
  end else
  if (~start_clr_l) begin
    brk_in_l_m <= 1'b1;
  end else
  if (~(brk_in_clk)) begin
    brk_in_l_m <= 1'b0;
  end
always @(brk_in_clk, n_t_32x, start_clr_l, brk_in_l_m)
  if (~n_t_32x) begin
    brk_in_l <= 1'b0;
  end else
  if (~start_clr_l) begin
    brk_in_l <= 1'b1;
  end else
  if (brk_in_clk) begin
    brk_in_l <= brk_in_l_m;
  end
// e49: sn7400 
assign hi_main_data_l = ~(main_data & bdata5);
assign n_t_7x = ~(n6rk3_ok_l & data_state_l);
assign hi_rd_clk = ~(rd_shft_db_l & hi_main_shft_l);
assign hi_data_in = ~(hi_main_data_l & data_in_l);
// open collector 'wire-or's 
assign bk_cycle_l = data_enable? ~data_enable: 1'bz;
assign brk_in_prog_l = nbr? ~nbr: 1'bz;
assign cpma_dis_l = nbr? ~nbr: 1'bz;
assign data_enab_l = device_rk? ~device_rk: 1'bz;
assign dsk_cyl_ad128_l = (~(strobe & crc4))? 1'b0: 1'bz;
assign dsk_cyl_ad16_l = (~(strobe & crc7))? 1'b0: 1'bz;
assign dsk_cyl_ad1_l = (~(crc11 & strobe))? 1'b0: 1'bz;
assign dsk_cyl_ad2_l = (~(crc10 & strobe))? 1'b0: 1'bz;
assign dsk_cyl_ad32_l = (~(strobe & crc6))? 1'b0: 1'bz;
assign dsk_cyl_ad4_l = (~(strobe & crc9))? 1'b0: 1'bz;
assign dsk_cyl_ad64_l = (~(crc5 & strobe))? 1'b0: 1'bz;
assign dsk_cyl_ad8_l = (~(crc8 & strobe))? 1'b0: 1'bz;
assign dsk_drive0_l = drive0_l? ~drive0_l: 1'bz;
assign dsk_drive1_l = drive1_l? ~drive1_l: 1'bz;
assign dsk_drive2_l = drive2_l? ~drive2_l: 1'bz;
assign dsk_drive3_l = drive3_l? ~drive3_l: 1'bz;
assign ema0_l = (data_enable & ema0)? 1'b0: 1'bz;
assign ema1_l = (ema1 & data_enable)? 1'b0: 1'bz;
assign ema2_l = (ema2 & data_enable)? 1'b0: 1'bz;
assign ma0_l = (mak & n_t_26x)? 1'b0: 1'bz;
assign ma10_l = (n_t_44x & mak)? 1'b0: 1'bz;
assign ma11_l = (mak & n_t_47x)? 1'b0: 1'bz;
assign ma1_l = (mak & n_t_37x)? 1'b0: 1'bz;
assign ma2_l = (n_t_38x & mak)? 1'b0: 1'bz;
assign ma3_l = (n_t_39x & mak)? 1'b0: 1'bz;
assign ma4_l = (mak & n_t_40x)? 1'b0: 1'bz;
assign ma5_l = (mak & n_t_43x)? 1'b0: 1'bz;
assign ma6_l = (n_t_41x & mak)? 1'b0: 1'bz;
assign ma7_l = (mak & n_t_48x)? 1'b0: 1'bz;
assign ma8_l = (n_t_42x & mak)? 1'b0: 1'bz;
assign ma9_l = (n_t_45x & mak)? 1'b0: 1'bz;
assign mams_load_cont_l = malc? ~malc: 1'bz;
assign md_dir_l = (data_enable & brk_dir_l)? 1'b0: 1'bz;
assign msir_dis_l = data_enable? ~data_enable: 1'bz;
assign priority = (nbr & ~ts4)? 1'b0: 1'bz;
endmodule