~/Verilog/bin/topld.pl M7105B
info: cpol_use ne cpol_use20_8axial
info: cpol_use ne cpol_use20_8axial
info: cpol_use ne cpol_use20_8axial
info: edge_top ne edge_con2
warning: making e/edge_top/ a connector
info: n8881n ne dil14
info: 74155n ne dil16
info: ds75451n ne dil08
info: ds75451n ne dil08
info: sp380n ne dil14
info: ds75452n ne dil08
info: ds75452n ne dil08
info: dec8271 ne dil16
info: 74161n ne dil16
info: 74h00n ne 7400n
info: dec8271 ne dil16
info: n8881n ne dil14
info: 74161n ne dil16
info: sp380n ne dil14
info: 74174n ne dil16
info: 7486n ne dil14
info: n8881n ne dil14
info: sp384n ne dil14
info: 7402n ne dil14
info: 7400n ne dil14
info: dec8271 ne dil16
info: 7400n ne dil14
info: sp380n ne dil14
info: 74h11n ne 7411n
info: 74h74n ne 7474n
info: 7400n ne dil14
info: 74h10n ne 7410n
info: n8881n ne dil14
info: 74h74n ne 7474n
info: 7400n ne dil14
info: 7404n ne dil14
info: 7404n ne dil14
info: n8881n ne dil14
info: 74h74n ne 7474n
info: 7440n ne dil14
info: 7402n ne dil14
info: 74h74n ne 7474n
info: 7400n ne dil14
info: ds75452n ne dil08
info: ds75452n ne dil08
info: n8881n ne dil14
info: 74161n ne dil16
info: 7452 ne dil14
info: edge_top ne edge_con2
warning: making f/edge_top/ a connector
info: edge_top ne edge_con2
warning: making h/edge_top/ a connector
info: edge_top ne edge_con2
warning: making j/edge_top/ a connector
info: quad ne edge_con8
warning: making omnibus/quad/ a connector
warning: making w1/r_eu_/ a connector
warning: making w2/r_eu_/ a connector
warning: making w3/r_eu_/ a connector
warning: making w4/r_eu_/ a connector
warning: making w5/r_eu_/ a connector
warning: non-bypass capacitor deleted: c31
warning: non-bypass capacitor deleted: c32
warning: non-bypass capacitor deleted: c33
warning: non-bypass capacitor deleted: c37
~/Verilog/bin/smaller.pl M7105B.PLD >vv || (rm vv; exit 1)
14 signals were removed:
  bdata2_l: !bdata2
  bint_strobe: int_strobe
  brk_enable: !brk_enable_l
  brk_in: !brk_in_l
  btp1: tp1
  bts2: !ts2
  bts4: !ts4
  data_enable_l: !data_enable
  last_brk_l: !last_brk
  malc_l: !malc
  n3v: 'b'1
  n_t_15x: !b_last_brk
  nbr_l: !nbr
  set_main_brk: !set_main_brk_l
~/Verilog/bin/smaller.pl vv >M7105BX.PLD || (rm M7105BX.PLD; exit 1)
0 signals were removed:
~/Verilog/bin/cupl2v.pl M7105BX.PLD >vv || (rm vv; exit 1)
mv vv M7105B.v
rm M7105BX.PLD